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A21 DEMODULATOR BLOCK DIAGRAM
(OPTION 300)
A21 DEMODULATOR BLOCK DIAGRAM
(OPTION 300)
sk7106b
POWER SUPPLY INPUTS
+15V F 1
Filter
+5V REG
REG
+15V F 2
Filter
+12.3V
REG
-15V F
Filter
-5V REG
REG
+15V
Filter
+2.5V
REG
+3.3V
REG
+5V A
Filter
-5V A
+15V
P1-14
+15V
P1-64
-15V
P1-13,63
-15V
P1-16,17,66
+5V
P1-67
-5V
P1-12,62
Filter
IAB 10-0
D7-0
SEL n
R/WEn
RSTn
STRBn
Dig_BUS_INTn
DATA
DATA Clock
Symbol Sync
TRIGGER
10 MHz
P1-24,25,26,27,29,36,74,76,77,78,79
P1-20,21,23,79,71,72,73
P1-33
P1-83
P1-32
P1-82
P1-35
P1-49
P1-50
P1-100
P1-85
P1-84
P1
80 MHz
Clock
SRAM
256k x 32
FLASH
128 x 32
FLASH
256 x 32
30 MHz
Clock
PATTERN TRIG IN (FRAME TRIG IN)
DATA IN
DATA CLOCK IN
SYMB SYNC IN
EVENT 1, 2
SYNC LOSS
NO DATA
MEAS END
Err OUT
TEST IN
BIT CLOCK IN
SPR FUZZY IN0
SPR FUZZY IN1
SUB_BIT OUT
DIG_BUS_INT1
D_RCV_TRG
16 BTT CLK (4.333 MHz)
TST BUS
2
4
6
8
10
16
4
22
2
P2
TRIGGER/GATE
FPGA
SYNC
FPGA
INTERFACE
Rear Panel
BBG
P6
P3
Clock
DATA
GATE
EXT Clock
EXT DATA
EXT GATE
FREQ REF
DATA_X1
DATA_R1
P10
P9
P8
P13
P12
P11
P7
PLL
26 MHz
VCXO_IN
DSP
DSP_TCLK0
DSP_INTn
DSP Emul
DOWN
CONVERTER
I/O BUS
DATA BUS
P16
IF IN
Down Converter
12
ADC
DAC
TRIGGER
PULSE
DELAY
FIFO
SERIAL
EPROM