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A5 DUAL ARBITRARY WAVEFORM GENERATOR BLOCK DIAGRAM (OPTION UND)
A5 DUAL ARBITRARY WAVEFORM GENERATOR BLOCK DIAGRAM (OPT UND)
POWER SUPPLY INPUTS
+15V
+10 VREF
ABUS
-1 VREF
-1 VREF
+32V
P2-9
P2-14,64
P2-16,66
P2-17,67
P2-12, 62
P2-13,63
P2-1,7,54,56
P2-22,28,34, 40,
46,69,75,81,
87,93 ,99
+5VA
+5.2V
-5.2V
-15V
ANALOG
COMMON
DIGITAL
COMMON
+10V
REF
sk73b
PLL_REF
F
RFCLK_DIV
75 T O 150 MHz
VCO
PLL_VCO_TUNE
FREQ SCALING
WF_CLK_DDS_LD
WF_CLK_DDS_LD
WF_CLK_DDS_UD
WF_CLK_DDS_UD
REFERENCE
DATA SWITCH
DATA SEQUENCER
PROCESSOR
CLOCK PLL
REF SELECT
&
DIVIDE
EXT_REF_DIV4
PLL_REF_CLK
EXT_REF_DEL
ARB_REF
PLL_REF
13 MHz_BBG
WAVEFORM
CLOCK
TUNING
WF_CLK
WF_CLK_DIV2
I_LATCH_CLK
Q_LATCH_CLK
WF_CLK
WF_CLK_DIV2
WF_CLK_DDS
WF_ CLK_RAM
NWF_CLK_DIV2
DIGITAL
SIGNAL
PROCESSOR
40 Mhz
CLK_IN
DATA BUS
VPPI_EN
VPPQ_EN
VPPI_EN
VPPQ_EN
MEMORY DATA BUS
P_RAM
512 Kbyte
FLASH
MEMORY
5 Mbyte
PLL_UNLK
PLL_UNLK
PLL_ON
CLOCK
SELECT
POL
LATCH
CLOCK IN
P2-50
EXT_CK_POL
DATA IN
P2-49
DATA
SELECT
SYNC IN
P2-100
SYNC
SELECT
SYNC_IN__POL
PATTER
TRIGGER
P1-4
TRIGGER
SELECT
PAT_TRIG__POL
CONTROL
LOGIC
(FPGA)
CONTROL
MEMORY
EVENT 1_OUT
EVENT 2_OUT
P1-8
P1-10
POL_LATCH_ENABLE
DATA_IN_POL
CON_TRISTATE
EXT_CLOCK
EXT_DATA
EXT_SYNC
PATTERIN_TRIG
I/O DATA BUS
I/O DATA BUS
NSGEND
SQADV
WFCNT
VPPI_EN
VPPQ_EN
14
WAVEFORM
I RAM
1 Mword
MEMORY DATA BUS
NWFCLK_DIV2
WFCLK_DIV2
I_LATCH_CLK
MEMORY DATA BUS
ABUS
P2-4
2X
16 Mhz
FILTERS
2.50 Khz
2.5 Mhz
8.0 MHz
FILTERS
2.50 Khz
2.5 Mhz
8.0 MHz
WAVEFORM
Q
DAC
AUD 2
P2--55
P2--53
J2
Q_OUT
I_OFFSET
Q_OFFSET
ADJ
DAC
I
OFFSET ADJUST
Q
OFFSET ADJUST
I
GAIN ADJUST
Q
GAIN ADJUST
I/O DATA BUS
CONN_TRISTATE
2X
16 Mhz
RECONSTRUCTION
RECONSTRUCTION
WAVEFORM
I
DAC
AUD 2
P2-6
P2-52
J1
I_0UT
I DATA
GENERATION
Q DATA
GENERATION
14
WAVEFORM
Q RAM
1 Mword
SEQUENCER
RAM
MEMORY
SEQUENCER
NWFCLK_DIV2
WFCLK_DIV2
PLL_ON
SQ_CLK0
SQ_CLK1
Q_LATCH_CLK
SQ_CLK0
SQ_CLK0+
SQ_CLK1
SQ_CLK1
I/O DATA
BUS
EEPROM
DATA
LATCHED
ADDRESS
LATCHED
DATA
CONTROL
LOGIC
PROCESSOR INTERFACE
P2 - 33
EXT_LSEL
EXT LSTROBE
P2-82
P2-83
EXT RD L WR
EXT RESET
P2-32
P2-24
IAB0
IAB1
P2-74
P2-25
IAB2
IAB3
P2 - 26
P2-76
IAB4
IAB5
P2-27
P2-77
IAB6
IAB7
P2-78
P2-29
IAB8
IAB9
P2-79
P2-36
IAB10
READ/LWRITE
STROBE
SELECT
RESET
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
P2-19
EXT_DO
EXT_D1
P2-20
P2-70
EXT_D2
EXT_D3
P2-21
P2-71
EXT_D4
EXT_D5
P2-72
P2-23
EXT_D6
P2-73
EXT_D7
D0
DIG BUS INT
(PLL UNLOCKED)
D1
D2
D3
D4
D5
D6
D7
SELECT
CLK
WFR_ARB
WFR_ARB
J3
WFCLK
EVENT 2
EVENT 2
EVENT 1
EVENT 1
USO_CLK 0
U
SO
_
CL
K
1