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TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
signal groups description
TRST
EXT_INT7
Clock/PLL
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Reset and
Interrupts
DMA Status
Power-Down
Status
Control/Status
TDI
TDO
TMS
TCK
CLKIN
CLKOUT1
CLKMODE0
PLLV
PLLG
PLLF
EMU1
EMU0
RSV2
RSV1
RSV0
NMI
IACK
INUM3
INUM2
INUM1
INUM0
DMAC3
DMAC2
DMAC1
DMAC0
PD
RSV4
RSV3
EXT_INT6
EXT_INT5
EXT_INT4
RESET
CLKOUT2
CLKMODE1
†
CLKMODE2
†
†
For GLS devices only
Figure 3. CPU Signals
ADVANCE INFORMATION