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TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
71
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 49)
NO.
’C6202-200
’C6202-233
’C6202-250
UNIT
MIN MAX
1 t
c(TCK)
Cycle time, TCK 50 ns
3 t
su(TDIV-TCKH)
Setup time, TDI/TMS/TRST valid before TCK high 10 ns
4 t
h(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high 5 ns
switching characteristics for JTAG test port (see Figure 49)
NO. PARAMETER
’C6202-200
’C6202-233
’C6202-250
UNIT
MIN MAX
2 t
d(TCKL-TDOV)
Delay time, TCK low to TDO valid 0 15 ns
TCK
TDO
TDI/TMS/TRST
1
2
3
4
2
Figure 49. JTAG Test-Port Timing
ADVANCE INFORMATION