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TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING
timing requirements with external device as asynchronous bus master
†
(see Figure 36 and
Figure 37)
NO. MIN MAX UNIT
1 t
w(XCSL)
Pulse duration, XCS low 4P ns
2 t
w(XCSH)
Pulse duration, XCS high 4P ns
3 t
su(XSEL-XCSL)
Setup time, expansion bus select signals
‡
valid before XCS low 2 ns
4 t
h(XCSL-XSEL)
Hold time, expansion bus select signals
‡
valid after XCS low 2 ns
10 t
h(XRYL-XCSL)
Hold time, XCS low after XRDY low P ns
11 t
su(XBEV-XCSH)
Setup time, XBE[3:0]/XA[5:2] valid before XCS high
§
2 ns
12 t
h(XCSH-XBEV)
Hold time, XBE[3:0]/XA[5:2] valid after XCS high
§
2 ns
13 t
su(XDV-XCSH)
Setup time, XDx valid before XCS high 2 ns
14 t
h(XCSH-XDV)
Hold time, XDx valid after XCS high 2 ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡
Expansion bus select signals include XCNTL and XR/W.
§
XBE[3:0]
/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
switching characteristics with external device as asynchronous bus master (see Figure 36 and
Figure 37)
NO. PARAMETER MIN MAX UNIT
5 t
d(XCSL-XDLZ)
Delay time, XCS low to XDx low impedance 0 ns
6 t
d(XCSH-XDIV)
Delay time, XCS high to XDx invalid 0 12 ns
7 t
d(XCSH-XDHZ)
Delay time, XCS high to XDx high impedance 12 ns
8 t
d(XRYL-XDV)
Delay time, XRDY low to XDx valid 0 4 ns
9 t
d(XCSH-XRYH)
Delay time, XCS high to XRDY high 0 12 ns
Word
99
7
685
7
685
4
3
4
3
4
3
4
3
4
3
4
3
XCS
XCNTL
XBE[3:0]
/XA[5:2]
†
XR/W
‡
XR/W
‡
XD[31:0]
XRDY
10
1
2
1
10
†
XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
‡
XW/R input/output polarity selected at boot
Figure 36. External Device as Asynchronous Master—Read
ADVANCE INFORMATION