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TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
64
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
87
6
21
CLKX
FSX
DX
DR
Figure 42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
ADVANCE INFORMATION