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TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)
BE
AD D1 D2 D3 D4
13
13
1211
10
9
8
7
6
5
44
3
3
22
1
1
XCLKIN
XAS
XW/R
†
XW/R
†
XBLAST
‡
XBE[3:0]
/XA[5:2]
§
XD[31:0]
XRDY
XWE
/XWAIT
¶
†
XW/R input/output polarity selected at boot
‡
XBLAST output polarity is always active low.
§
XBE[3:0]
/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
¶
XWE
/XWAIT operates as XWAIT output signal during host-port accesses.
Figure 33. ’C6202 as Bus Master—Read
Addr D1 D2 D3 D4
13
13
1211
8
7
6
5
44
3
3
22
1
1
XCLKIN
XAS
XW/R
†
XW/R
†
XBLAST
‡
XBE[3:0]
/XA[5:2]
§
XD[31:0]
XRDY
XWE
/XWAIT
¶
†
XW/R input/output polarity selected at boot
‡
XBLAST output polarity is always active low.
§
XBE[3:0]
/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
¶
XWE
/XWAIT operates as XWAIT output signal during host-port accesses.
Figure 34. ’C6202 as Bus Master—Write
ADVANCE INFORMATION