Filter
Top Products
TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS FIFO TIMING
timing requirements for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)
NO. MIN MAX UNIT
5 t
su(XDV-XFCKH)
Setup time, read XDx valid before XFCLK high 2.5 ns
6 t
h(XFCKH-XDV)
Hold time, read XDx valid after XFCLK high 2 ns
switching characteristics for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28)
NO. PARAMETER MIN MAX UNIT
1 t
d(XFCKH-XCEV)
Delay time, XFCLK high to XCEx valid 1.5 5.2 ns
2 t
d(XFCKH-XAV)
Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid
†
1.5 5.2 ns
3 t
d(XFCKH-XOEV)
Delay time, XFCLK high to XOE valid 1.5 5.2 ns
4 t
d(XFCKH-XREV)
Delay time, XFCLK high to XRE valid 1.5 5.2 ns
7 t
d(XFCKH-XWEV)
Delay time, XFCLK high to XWE/XWAIT
‡
valid 1.5 5.2 ns
8 t
d(XFCKH-XDV)
Delay time, XFCLK high to XDx valid 5.2 ns
9 t
d(XFCKH-XDIV)
Delay time, XFCLK high to XDx invalid 1.5 ns
†
XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.
‡
XWE
/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.
XA1 XA2 XA3 XA4
D1 D2 D3 D4
6
5
44
33
22
11
XFCLK
XCE3
†
XBE[3:0]
/XA[5:2]
‡
XOE
XRE
XWE/XWAIT
§
XD[31:0]
†
FIFO read (glueless) mode only available in XCE3.
‡
XBE[3:0]
/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.
§
XWE
/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.
Figure 26. FIFO Read Timing (Glueless Read Mode)
ADVANCE INFORMATION