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TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
XHOLD/XHOLDA TIMING (CONTINUED)
switching characteristics for expansion bus arbitration (internal arbiter disabled)
†
(see Figure 39)
NO. PARAMETER MIN MAX UNIT
1 t
d(XHDAH-XBLZ)
Delay time, XHOLDA high to XBus low impedance
‡
2P 2P + 10 ns
2 t
d(XBHZ-XHDL)
Delay time, XBus high impedance to XHOLD low
‡
0 2P ns
†
P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡
XBus consists of XBE[3:0]
/XA[5:2], XAS, XW/R, and XBLAST.
C6202
1
2
XHOLD (output)
XHOLDA (input)
XBus
†
†
XBus consists of XBE[3:0]
/XA[5:2], XAS, XW/R, and XBLAST.
Figure 39. Expansion Bus Arbitration—Internal Arbiter Disabled
ADVANCE INFORMATION