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TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
RESET TIMING (CONTINUED)
1
22
109
87
43
CLKOUT1
RESET
CLKOUT2
HIGH GROUP
†
LOW GROUP
†
Z GROUP
†
65
12
11
XD[31:0]
‡
†
High group consists of: XFCLK
Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,
FSR2, XCE[3:0]
, XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,
and XHOLDA.
‡
XD[31:0] are the boot configuration pins during device reset.
Figure 24. Reset Timing
ADVANCE INFORMATION