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TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)
timing requirements with ’C6202 as bus master (see Figure 33, Figure 34, and Figure 35)
NO. MIN MAX UNIT
9 t
su(XDV-XCKIH)
Setup time, XDx valid before XCLKIN high 4 ns
10 t
h(XCKIH-XDV)
Hold time, XDx valid after XCLKIN high 2.3 ns
11 t
su(XRY-XCKIH)
Setup time, XRDY valid before XCLKIN high
†
4 ns
12 t
h(XCKIH-XRY)
Hold time, XRDY valid after XCLKIN high
†
2.3 ns
14 t
su(XBFF-XCKIH)
Setup time, XBOFF valid before XCLKIN high 4 ns
15 t
h(XCKIH-XBFF)
Hold time, XBOFF valid after XCLKIN high 2.3 ns
†
XRDY operates as active-low ready input/output during host-port accesses.
switching characteristics with ’C6202 as bus master (see Figure 33, Figure 34, and Figure 35)
NO. PARAMETER MIN MAX UNIT
1 t
d(XCKIH-XASV)
Delay time, XCLKIN high to XAS valid 5 15.5 ns
2 t
d(XCKIH-XWRV)
Delay time, XCLKIN high to XW/R valid
‡
5 15.5 ns
3 t
d(XCKIH-XBLTV)
Delay time, XCLKIN high to XBLAST valid
§
5 15.5 ns
4 t
d(XCKIH-XBEV)
Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid
¶
5 15.5 ns
5 t
d(XCKIH-XDLZ)
Delay time, XCLKIN high to XDx low impedance 5 ns
6 t
d(XCKIH-XDV)
Delay time, XCLKIN high to XDx valid 15.5 ns
7 t
d(XCKIH-XDIV)
Delay time, XCLKIN high to XDx invalid 5 ns
8 t
d(XCKIH-XDHZ)
Delay time, XCLKIN high to XDx high impedance 18 ns
13 t
d(XCKIH-XWTV)
Delay time, XCLKIN high to XWE/XWAIT valid
#
5 15.5 ns
‡
XW/R input/output polarity selected at boot.
§
XBLAST output polarity is always active low.
¶
XBE[3:0]
/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
#
XWE
/XWAIT operates as XWAIT output signal during host-port accesses.
ADVANCE INFORMATION