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TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING
timing requirements for asynchronous peripheral cycles
†
(see Figure 29–Figure 30)
NO.
’C6202-200
’C6202-233
’C6202-250
UNIT
MIN MAX
4 t
su(XDV-CKO1H)
Setup time, read XDx valid before CLKOUT1 high 4.0 ns
5 t
h(CKO1H-XDV)
Hold time, read XDx valid after CLKOUT1 high 0 ns
8 t
su(XRY-CKO1H)
Setup time, XRDY valid before CLKOUT1 high 4.0 ns
9 t
h(CKO1H-XRY)
Hold time, XRDY valid after CLKOUT1 high 0 ns
†
To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input.
switching characteristics for asynchronous peripheral cycles
द
(see Figure 29–Figure 30)
NO. PARAMETER
’C6202-200
’C6202-233
’C6202-250
UNIT
MIN MAX
1 t
d(CKO1H-XCEV)
Delay time, CLKOUT1 high to XCEx valid 0 4.0 ns
2 t
d(CKO1H-XAV)
Delay time, CLKOUT1 high to XBE[3:0]/XA[5:2] valid 0 4.0 ns
3 t
d(CKO1H-XAIV)
Delay time, CLKOUT1 high to XBE[3:0]/XA[5:2] invalid 0 4.0 ns
6 t
d(CKO1H-XOEV)
Delay time, CLKOUT1 high to XOE valid 0 4.0 ns
7 t
d(CKO1H-XREV)
Delay time, CLKOUT1 high to XRE valid 0 4.0 ns
10 t
d(CKO1H-XDV)
Delay time, CLKOUT1 high to XDx valid 4.0 ns
11 t
d(CKO1H-XDIV)
Delay time, CLKOUT1 high to XDx invalid 0 ns
12 t
d(CKO1H-XWEV)
Delay time, CLKOUT1 high to XWE/XWAIT valid 0 4.0 ns
‡
The minimum delay is also the minimum output hold after CLKOUT1 high.
§
XBE[3:0]
/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses.
¶
XWE
/XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses.
ADVANCE INFORMATION