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4.15Inter-IntegratedCircuitSerialPorts(I2C0,I2C1)
4.15.1I2CDevice-SpecificInformation
Peripheral
Configuration
Bus
Noise
Filter
Noise
Filter
Clock Prescaler
I2CPSCx
Prescaler
Register
Bit Clock Generator
I2CCLKHx
Clock Divide
High Register
I2CCLKLx
Clock Divide
Low Register
Control
I2CCOARx
Own Address
Register
I2CSARx
Slave Address
Register
I2CCMDRx Mode Register
I2CEMDRx
Extended Mode
Register
I2CCNTx
Data Count
Register
I2CPID1
Peripheral ID
Register 1
I2CPID2
Peripheral ID
Register 2
Transmit
I2CXSRx
Transmit Shift
Register
I2CDXRx Transmit Buffer
Receive
I2CDRRx
Receive Buffer
I2CRSRx
Receive Shift
Register
I2Cx_SCL
I2Cx_SDA
C672x I2C Module
Control
Interrupt/DMA
I2CIERx
Interrupt Enable
Register
I2CSTRx
Interrupt Status
Register
I2CSRCx
Interrupt Source
Register
Control
I2CPFUNC
Pin Function
Register
I2CPDIR
Pin Direction
Register
I2CPDIN
Pin Data In
Register
I2CPDOUT
Pin Data Out
Register
I2CPDSET
Pin Data Set
Register
I2CPDCLR
Pin Data Clear
Register
Interrupt DMA
Requests
TMS320C6727,TMS320C6726,TMS320C6722
Floating-PointDigitalSignalProcessors
SPRS268E–MAY2005–REVISEDJANUARY2007
HavingtwoI2CmodulesontheC672xsimplifiessystemarchitecture,sinceonemodulemaybeusedby
theDSPtocontrollocalperipheralsICs(DACs,ADCs,etc.)whiletheothermaybeusedtocommunicate
withothercontrollersinasystemortoimplementauserinterface.Figure4-37isblockdiagramofthe
C672xI2CModule.
EachI2Cportsupports:
•CompatiblewithPhilips
®
I2CSpecificationRevision2.1(January2000)
•FastModeupto400Kbps(nofail-safeI/Obuffers)
•NoiseFiltertoRemoveNoise50nsorless
•Seven-andTen-BitDeviceAddressingModes
•Master(Transmit/Receive)andSlave(Transmit/Receive)Functionality
•Events:DMA,Interrupt,orPolling
•General-PurposeI/OCapabilityifnotusedasI2C
CAUTION
TheC672xI2Cpinsuseastandard±8mALVCMOSbuffer,nottheslowI/Obuffer
definedintheI2Cspecification.Seriesresistorsmaybenecessarytoreducenoiseat
thesystemlevel.
Figure4-37.I2CModuleBlockDiagram
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