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4.11.3EMIFElectricalData/Timing
TMS320C6727,TMS320C6726,TMS320C6722
Floating-PointDigitalSignalProcessors
SPRS268E–MAY2005–REVISEDJANUARY2007
Table4-5throughTable4-8assumetestingoverrecommendedoperatingconditions(seeFigure4-7
throughFigure4-13).
Table4-5.EMIFSDRAMInterfaceTimingRequirements
NO.MINMAXUNIT
19t
su(EM_DV-EM_CLKH)
Inputsetuptime,readdatavalidonD[31:0]beforeEM_CLKrising3ns
20t
h(EM_CLKH-EM_DIV)
Inputholdtime,readdatavalidonD[31:0]afterEM_CLKrising1.9ns
Table4-6.EMIFSDRAMInterfaceSwitchingCharacteristics
NO.PARAMETERMINMAXUNIT
1t
c(EM_CLK)
Cycletime,EMIFclockEM_CLK10ns
2t
w(EM_CLK)
Pulsewidth,EMIFclockEM_CLKhighorlow3ns
3t
d(EM_CLKH-EM_CSV)S
Delaytime,EM_CLKrisingtoEM_CS[0]valid7.7ns
4t
oh(EM_CLKH-EM_CSIV)S
Outputholdtime,EM_CLKrisingtoEM_CS[0]invalid1.15ns
5t
d(EM_CLKH-EM_WE-DQMV)S
Delaytime,EM_CLKrisingtoEM_WE_DQM[3:0]valid7.7ns
6t
oh(EM_CLKH-EM_WE-DQMIV)S
Outputholdtime,EM_CLKrisingtoEM_WE_DQM[3:0]invalid1.15ns
7t
d(EM_CLKH-EM_AV)S
Delaytime,EM_CLKrisingtoEM_A[12:0]andEM_BA[1:0]valid7.7ns
Outputholdtime,EM_CLKrisingtoEM_A[12:0]andEM_BA[1:0]
8t
oh(EM_CLKH-EM_AIV)S
1.15ns
invalid
9t
d(EM_CLKH-EM_DV)S
Delaytime,EM_CLKrisingtoEM_D[31:0]valid7.7ns
10t
oh(EM_CLKH-EM_DIV)S
Outputholdtime,EM_CLKrisingtoEM_D[31:0]invalid1.15ns
11t
d(EM_CLKH-EM_RASV)S
Delaytime,EM_CLKrisingtoEM_RASvalid7.7ns
12t
oh(EM_CLKH-EM_RASIV)S
Outputholdtime,EM_CLKrisingtoEM_RASinvalid1.15ns
13t
d(EM_CLKH-EM_CASV)S
Delaytime,EM_CLKrisingtoEM_CASvalid7.7ns
14t
oh(EM_CLKH-EM_CASIV)S
Outputholdtime,EM_CLKrisingtoEM_CASinvalid1.15ns
15t
d(EM_CLKH-EM_WEV)S
Delaytime,EM_CLKrisingtoEM_WEvalid7.7ns
16t
oh(EM_CLKH-EM_WEIV)S
Outputholdtime,EM_CLKrisingtoEM_WEinvalid1.15ns
17t
dis(EM_CLKH-EM_DHZ)S
Delaytime,EM_CLKrisingtoEM_D[31:0]3-stated7.7ns
18t
ena(EM_CLKH-EM_DLZ)S
Outputholdtime,EM_CLKrisingtoEM_D[31:0]driving1.15ns
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