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TMS320C6727,TMS320C6726,TMS320C6722
Floating-PointDigitalSignalProcessors
SPRS268E–MAY2005–REVISEDJANUARY2007
Thefivebusmastersarbitrateforfivedifferenttargetgroups:
T1On-chipmemoriesthroughtheCPUSlavePort(CSP).
T2Memoriesontheexternalmemoryinterface(EMIF).
T3Peripheralregistersthroughtheperipheralconfigurationbus.
T4McASPserializersthroughthededicatedMcASPDMAbus.
T5dMAXregisters.
Thecrossbarswitchsupportsparallelaccessesfromdifferentbusmasterstodifferenttargets.Whentwo
ormorebusmasterscontendforthesametargetbeginningatthesamecycle,thenthehighest-priority
masterisgivenownershipofthetargetwhiletheothermaster(s)arestalled.However,onceownershipof
thetargetisgiventoabusmaster,itisallowedtocompleteitsaccessbeforeownershipisarbitrated
again.Followingaretwoexamples.
Example1:Simultaneousaccesseswithoutconflict
•dMAXHiMAXaccessesMcASPDataPortfortransferofaudiodata.
•dMAXLoMAXaccessesSPIportforcontrolprocessing.
•UHPIaccessesinternalRAMthroughtheCSP.
•CPUfillsprogramcachefromEMIF.
Example2:Conflictoverasharedresource
•dMAXHiMAXaccessesRTIportforMcASPsampleratemeasurement.
•dMAXLoMAXaccessesSPIportforcontrolprocessing.
InExample2,bothmasterscontendforthesametarget,theperipheralconfigurationbus.TheHiMAX
accesswillbegivenpriorityovertheLoMAXaccess.
ThemasterpriorityisillustratedinFigure2-4bythenumbers1through4inthebusarbitersymbols.Note
thattheEMIFarbitrationisdistributedsothatonlyonebridgecrossingisnecessaryforPMPaccesses.
TheeffectisthatPMPhas5thprioritytotheEMIFbutlowerlatency.
Abusbridgeisneededbetweenmastersandtargetswhichrunatdifferentclockrates.Thebusbridge
containsasmallFIFOtoallowthebridgetoacceptanincoming(burst)accessatoneclockrateandpass
itthroughthebridgetoatargetrunningatadifferentrate.Table2-6liststheFIFOpropertiesofthefour
bridges(BR1,BR2,BR3,andBR4)inFigure2-4.
Table2-6.BusBridges
LABELBRIDGEDESCRIPTIONMASTERCLOCKTARGETCLOCK
BR1DMPBridgetoperipherals,dMAX,EMIFSYSCLK1SYSCLK2
BR2dMAX,UHPItoROM/RAM(CSP)SYSCLK2SYSCLK1
BR3PMPtoEMIFSYSCLK1SYSCLK3
BR4CPU,UHPI,anddMAXtoEMIFSYSCLK2SYSCLK3
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