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1.2Description
TMS320C6727,TMS320C6726,TMS320C6722
Floating-PointDigitalSignalProcessors
SPRS268E–MAY2005–REVISEDJANUARY2007
TheTMS320C672xisthenextgenerationofTexasInstruments'C67xgenerationofhigh-performance
32-/64-bitfloating-pointdigitalsignalprocessors.TheTMS320C672xincludestheTMS320C6727,
TMS320C6726,andTMS320C6722devices.
(1)
EnhancedC67x+CPU.TheC67x+CPUisanenhancedversionoftheC67xCPUusedontheC671x
DSPs.ItiscompatiblewiththeC67xCPUbutofferssignificantimprovementsinspeed,codedensity,and
floating-pointperformanceperclockcycle.At300MHz,theCPUiscapableofamaximumperformanceof
2400MIPS/1800MFLOPSbyexecutinguptoeightinstructions(sixofwhicharefloating-point
instructions)inparalleleachcycle.TheCPUnativelysupports32-bitfixed-point,32-bitsingle-precision
floating-point,and64-bitdouble-precisionfloating-pointarithmetic.
EfficientMemorySystem.Thememorycontrollermapsthelargeon-chip256K-byteRAMand384K-byte
ROMasunifiedprogram/datamemory.Developmentissimplifiedsincethereisnofixeddivisionbetween
programanddatamemorysizeasonsomeotherdevices.
Thememorycontrollersupportssingle-cycledataaccessesfromtheC67x+CPUtotheRAMandROM.
UptothreeparallelaccessestotheinternalRAMandROMfromthreeofthefollowingfoursourcesare
supported:
•Two64-bitdataaccessesfromtheC67x+CPU
•One256-bitprogramfetchfromthecoreandprogramcache
•One32-bitdataaccessfromtheperipheralsystem(eitherdMAXorUHPI)
Thelarge(32K-byte)programcachetranslatestoahighhitrateformostapplications.Thispreventsmost
program/dataaccessconflictstotheon-chipmemory.Italsoenableseffectiveprogramexecutionfroman
off-chipmemorysuchasanSDRAM.
High-PerformanceCrossbarSwitch.Ahigh-performancecrossbarswitchactsasacentralhubbetween
thedifferentbusmasters(CPU,dMAX,UHPI)anddifferenttargets(peripheralsandmemory).The
crossbarispartiallyconnected;someconnectionsarenotsupported(forexample,UHPI-to-peripheral
connections).
Multipletransfersoccurinparallelthroughthecrossbaraslongasthereisnoconflictbetweenbus
mastersforaparticulartarget.Whenaconflictdoesoccur,thearbitrationisasimpleanddeterministic
fixed-priorityscheme.
ThedMAXisgivenhighest-prioritysinceitisresponsibleforthemosttime-criticalI/Otransfers,followed
nextbytheUHPI,andfinallybytheCPU.
dMAXDualDataMovementAccelerator.ThedMAXisamoduledesignedtoperformDataMovement
Acceleration.TheDataMovementAccelerator(dMAX)controllerhandlesuser-programmeddatatransfers
betweentheinternaldatamemorycontrollerandthedeviceperipheralsontheC672xDSPs.ThedMAX
allowsmovementofdatato/fromanyaddressablememoryspaceincludinginternalmemory,peripherals,
andexternalmemory.
ThedMAXcontrollerincludesfeaturessuchasthecapabilitytoperformthree-dimensionaldatatransfers
foradvanceddatasorting,andthecapabilitytomanageasectionofthememoryasacircularbuffer/FIFO
withdelay-tapbasedreadingandwritingofdata.ThedMAXcontrolleriscapableofconcurrently
processingtwotransferrequests(providedthattheyareto/fromdifferentsource/destinations).
ExternalMemoryInterface(EMIF)forFlexibilityandExpansion.Theexternalmemoryinterfaceonthe
C672xsupportsasinglebankofSDRAMandasinglebankofasynchronousmemory.TheEMIFdata
widthis16bitswideontheC6726andC6722,and32bitswideontheC6727.
SDRAMsupportincludesx16andx32SDRAMdeviceswith1,2,or4banks.
TheC6726andC6722supportSDRAMdevicesupto128Mbits.
(1)Throughouttheremainderofthedocument,TMS320C6727(orC6727),TMS320C6726(orC6726),and/orTMS320C6722(orC6722)
willbereferredtoasTMS320C672x(orC672x).
TMS320C6727,TMS320C6726,TMS320C6722DSPs 2SubmitDocumentationFeedback