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UHF (7640) CIRCUIT DESCRIPTION
5B-10
November 1998
Part No. 001-7600-001
Figure 5-6 PLL Circuit (UHF)
5.6.5 APC CIRCUIT
The APC (Automatic Power Control) circuit pro-
tects the power amplifier from damage caused by a
mismatched antenna load, and provides a stable power
output.
One diode in D1 detects forward signals and the
other detects reverse signals. The combined voltage is
at minimum level when a matched antenna load of 50
ohms is present and then increases as it becomes mis-
matched. The detected voltage is applied to pin 6 of
inverse amplifier IC4b. Power setting voltage T4 is
applied to the other input (pin 5) as a reference.
When antenna impedance is mismatched, the
detected voltage exceeds the power setting voltage.
The output voltage on pin 7 then decreases which
turns Q17 off slightly. Transistor Q18 then turns off
slightly and lowers the voltage applied to the collec-
tor of Q19 and the power control input of IC5. This
reduces the output power produced by these devices.
5.7 UHF PLL CIRCUIT
5.7.1 PLL CIRCUIT
The PLL (Phase-Locked-Loop) circuit provides a
stable (± 2.5 PPM) receive first injection and transmit
frequency. The PLL circuit consists of PLL circuit
IC2, a loop filter, and reference oscillator. A block
diagram of the PLL circuit is shown in Figure 5-6.
The signal from VCOs (Voltage-Controlled
Oscillator) Q23 and Q25 is buffered by Q28 and Q29
and then applied to pin 2 of IC10. The prescaler in
IC10 divides the VCO signal down so that it is within
the frequency range of the programmable counter.
A reference frequency generated by reference
oscillator X2 is applied to pin 15 of IC1. This signal is
divided down by a programmable divider and pro-
vides the reference input to the phase detector. When
the VCO is oscillating at the correct frequency, the
VCO-derived input to the phase detector is the same
frequency as the reference input.