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DSP
Digital Signal Processing.
DTB arbitration bus
The VT1432A does not use the arbitration bus. The arbitration bus is part of the
VXI specification and is used by some modules to request bus control.
ECL
Emitter-Collector Logic, a standard for electrical signals.
Engineering Unit (EU)
A scale factor used to convert the output of a transducer (in volts) into another
unit (for example: g’s).
FFT
Fast Fourier Transform.
FIFO
First-In First-Out. A buffer and controller used to transmit data. The FIFO in the
VT1432A/33B input is implemented using DRAM.
freerun counter
A counter in which the bits always increment. When the freerun counter reaches
all ones it resets to all zeros and continues counting.
Fs
Sample Frequency or sample rate.
group ID
Any number of channels may be declared and uniquely identified by a groupID.
A channel can be a member of more than one group.
holdoff time
A circuit that detects a trigger signal will not respond to another trigger until the
holdoff time has passed. This prevents a ringing signal from be detected as
multiple triggers.
IACK
Interrupt ACKnowledge.
ICP
®
Integrated-Circuit Piezo-electric transducer.
IRQ
Interrupt ReQuest.
VT1433B User's Guide
Glossary
G-3