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4.14.3SPIElectricalData/Timing
TMS320C6727,TMS320C6726,TMS320C6722
Floating-PointDigitalSignalProcessors
SPRS268E–MAY2005–REVISEDJANUARY2007
4.14.3.1SerialPeripheralInterface(SPI)Timing
Table4-25throughTable4-32assumetestingoverrecommendedoperatingconditions(seeFigure4-33
throughFigure4-36).
Table4-25.GeneralTimingRequirementsforSPIxMasterModes
(1)
NO.MINMAXUNIT
greaterof8Por
1t
c(SPC)M
CycleTime,SPIx_CLK,AllMasterModes256Pns
100ns
2t
w(SPCH)M
PulseWidthHigh,SPIx_CLK,AllMasterModesgreaterof4Por45nsns
3t
w(SPCL)M
PulseWidthLow,SPIx_CLK,AllMasterModesgreaterof4Por45nsns
Polarity=0,Phase=0,
4P
toSPIx_CLKrising
Polarity=0,Phase=1,
0.5t
c(SPC)M
+4P
Delay,initialdatabitvalid
toSPIx_CLKrising
4t
d(SIMO_SPC)M
onSPIx_SIMOtoinitialns
Polarity=1,Phase=0,
edgeonSPIx_CLK
(2)
4P
toSPIx_CLKfalling
Polarity=1,Phase=1,
0.5t
c(SPC)M
+4P
toSPIx_CLKfalling
Polarity=0,Phase=0,
15
fromSPIx_CLKrising
Polarity=0,Phase=1,
15
Delay,subsequentbits
fromSPIx_CLKfalling
5t
d(SPC_SIMO)M
validonSPIx_SIMOafterns
Polarity=1,Phase=0,
transmitedgeofSPIx_CLK
15
fromSPIx_CLKfalling
Polarity=1,Phase=1,
15
fromSPIx_CLKrising
Polarity=0,Phase=0,
0.5t
c(SPC)M
–10
fromSPIx_CLKfalling
Polarity=0,Phase=1,
Outputholdtime,
0.5t
c(SPC)M
–10
fromSPIx_CLKrising
SPIx_SIMOvalidafter
6t
oh(SPC_SIMO)M
ns
receiveedgeofSPIxCLK,
Polarity=1,Phase=0,
0.5t
c(SPC)M
–10
exceptforfinalbit
(3)
fromSPIx_CLKrising
Polarity=1,Phase=1,
0.5t
c(SPC)M
–10
fromSPIx_CLKfalling
Polarity=0,Phase=0,
0.5P+15
toSPIx_CLKfalling
Polarity=0,Phase=1,
0.5P+15
InputSetupTime,
toSPIx_CLKrising
7t
su(SOMI_SPC)M
SPIx_SOMIvalidbeforens
Polarity=1,Phase=0,
receiveedgeofSPIx_CLK
0.5P+15
toSPIx_CLKrising
Polarity=1,Phase=1,
0.5P+15
toSPIx_CLKfalling
Polarity=0,Phase=0,
0.5P+5
fromSPIx_CLKfalling
Polarity=0,Phase=1,
0.5P+5
InputHoldTime,
fromSPIx_CLKrising
8t
ih(SPC_SOMI)M
SPIx_SOMIvalidafterns
Polarity=1,Phase=0,
receiveedgeofSPIx_CLK
0.5P+5
fromSPIx_CLKrising
Polarity=1,Phase=1,
0.5P+5
fromSPIx_CLKfalling
(1)P=SYSCLK2period
(2)FirstbitmaybeMSBorLSBdependinguponSPIconfiguration.MO(0)referstofirstbitandMO(n)referstolastbitoutputon
SPIx_SIMO.MI(0)referstothefirstbitinputandMI(n)referstothelastbitinputonSPIx_SOMI.
(3)ThefinaldatabitwillbeheldontheSPIx_SIMOpinuntiltheSPIDAT0orSPIDAT1registeriswrittenwithnewdata.
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