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2.7MemoryMapSummary
TMS320C6727,TMS320C6726,TMS320C6722
Floating-PointDigitalSignalProcessors
SPRS268E–MAY2005–REVISEDJANUARY2007
Ahigh-levelmemorymapoftheC672xDSPappearsinTable2-8.Thebaseaddressofeachregionis
listed.Anyaddresspasttheendaddressmustnotbereadorwritten.Thetablealsolistswhetherthe
regionsareword-addressableorbyte-andword-addressable.
Table2-8.C672xMemoryMap
DESCRIPTIONBASEADDRESSENDADDRESSBYTE-ORWORD-ADDRESSABLE
InternalROMPage0(256KBytes)0x000000000x0003FFFFByteandWord
InternalROMPage1(128KBytes)0x000400000x0005FFFFByteandWord
InternalRAMPage0(256KBytes)0x100000000x1003FFFFByteandWord
MemoryandCacheControlRegisters0x200000000x2000001FWordOnly
EmulationControlRegisters(DoNotAccess)0x300000000x3FFFFFFFWordOnly
DeviceConfigurationRegisters0x400000000x40000083WordOnly
PLLControlRegisters0x410000000x4100015FWordOnly
Real-timeInterrupt(RTI)ControlRegisters0x420000000x420000A3WordOnly
UniversalHost-PortInterface(UHPI)Registers0x430000000x43000043WordOnly
McASP0ControlRegisters0x440000000x440002BFWordOnly
McASP1ControlRegisters0x450000000x450002BFWordOnly
McASP2ControlRegisters0x460000000x460002BFWordOnly
SPI0ControlRegisters0x470000000x4700007FWordOnly
SPI1ControlRegisters0x480000000x4800007FWordOnly
I2C0ControlRegisters0x490000000x4900007FWordOnly
I2C1ControlRegisters0x4A0000000x4A00007FWordOnly
McASP0DMAPort(anyaddressinthisrange)0x540000000x54FFFFFFWordOnly
McASP1DMAPort(anyaddressinthisrange)0x550000000x55FFFFFFWordOnly
McASP2DMAPort(anyaddressinthisrange)0x560000000x56FFFFFFWordOnly
dMAXControlRegisters0x600000000x6000008FWordOnly
MAX0(HiMAX)EventEntryTable0x610080000x6100807FByteandWord
Reserved0x610080800x6100809F
MAX0(HiMAX)TransferEntryTable0x610080A00x610081FFByteandWord
MAX1(LoMAX)EventEntryTable0x620080000x6200807FByteandWord
Reserved0x620080800x6200809F
MAX1(LoMAX)TransferEntryTable0x620080A00x620081FFByteandWord
ExternalSDRAMspaceonEMIF0x800000000x8FFFFFFFByteandWord
ExternalAsynchronous/FlashspaceonEMIF0x900000000x9FFFFFFFByteandWord
EMIFControlRegisters0xF00000000xF00000BFWordOnly
(1)
(1)TheupperbyteoftheEMIF’sSDRAMConfigurationRegister(SDCR[31:24])isbyte-addressabletosupportplacingtheEMIFintothe
Self-RefreshStatewithouttriggeringtheSDRAMInitializationSequence.
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