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EM_CS[0]
EM_CAS
EM_RAS
EM_WE
EM_CLK
EM_CKE
EM_BA[1:0]
EM_A[11:0]
EM_WE_DQM[0]
EM_WE_DQM[1]
EM_D[15:0]
EM_CS[2]
EM_RW
EM_OE
GPIO
(6 Pins)RESET
C6726/C6722
DSP EMIF
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
2M x 16 x 4 Bank
SDRAM
A[18:13]
RY/BY
RESET
OE
WE
CE
DQ[15:0]
512K x 16
A[0]
A[12:1]
FLASH
EM_BA[1]
RESET
Any GPIO-capable pins which
can be pulled down at reset
can be used to control A[18:13]
for FLASH BOOTLOAD
Examples: AHCLKR0, SPI0_SCS
/SCL1
TMS320C6727,TMS320C6726,TMS320C6722
Floating-PointDigitalSignalProcessors
SPRS268E–MAY2005–REVISEDJANUARY2007
Figure4-5.C6726/C6722DSP16-BitEMIFExample
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