Filter
Top Products
www.ti.com
EM_D[31:16]/UHPI_HA[15:0]
(A)
UHPI_HCNTL[1:0]
UHPI_HD[15:0]
UHPI_HD[16]/HHWIL
UHPI_HD[31:17]
UHPI_HAS
(B)
UHPI_HBE[1:0]
(C)
UHPI_HRW
UHPI_HDS[2]
(G)
UHPI_HDS[1]
(G)
UHPI_HCS
UHPI_HRDY
AMUTE2/HINT
NC or GPIO
NC
A[x:y]
(D)
D[15:0]
A[1]
(E)
BE[1:0]
(F)
R/W
WE
(G)
RD
(G)
CS
RDY
INTERRUPT
DSP External Host MCU
TMS320C6727,TMS320C6726,TMS320C6722
Floating-PointDigitalSignalProcessors
SPRS268E–MAY2005–REVISEDJANUARY2007
Figure4-15illustratestheMultiplexedHostAddress/DataHalf-WordModehookupbetweentheC672x
DSPandanexternalhostmicrocontroller.Inthismode,each32-bitHPIaccessisbrokenupintotwo
halves.TheUHPI_HD[16]/HHWILpinfunctionsasUHPI_HHWILwhichmustbe'0'duringthefirsthalfof
accessand'1'duringthesecondhalf.
CAUTION
Unlessconfiguredasgeneral-purposeI/OintheUHPImodule,UHPI_HD[31:17]and
UHPI_HD[16]/HHWILwillbedrivenasoutputsalongwithUHPI_HD[15:0]whentheHPI
isread,eventhoughonlythelowerhalf-wordisusedtotransferdata.Thiscanbe
especiallyproblematicfortheUHPI_HD[16]/HHWILpinwhichshouldbeusedasan
inputinthismode.Therefore,besuretoconfiguretheupperhalfoftheUHPI_HDbus
asgeneral-purposeI/Opins.Furthermore,besuretoprogramtheUHPI_HD[16]
functionasageneral-purposeinputtoavoidadriveconflictwiththeexternalhost
MCU.
Inthismode,aswellastheMultiplexedHostAddress/DataFullwordmode,theUHPIcanbemademore
securebyrestrictingtheupper16bitsoftheDSPaddressesitcanaccesstowhatissetinCFGHPIAMSB
andCFGHPIAUMBregisters.(SeeTable4-13andTable4-14).
ThehostisresponsibleforconfiguringtheinternalHPIAregisterwhetherornotitisbeingoverriddenby
thedeviceconfigurationregistersCFGHPIAMSBandCFGHPIAUMB.
AftertheHPIAregisterhasbeenset,eitherasingleoragroupofautoincrementingaccessestoHPID
maybeperformed.
TheUHPI_HRDYaddswaitstatestoextendthehostMCUaccessuntiltheC672xDSPhascompleted
thedesiredoperation.
TheHINTsignalisavailablefortheDSPtointerruptthehostMCU.TheUHPIalsoincludesaninterruptto
theDSPcorefromthehostaspartoftheHPICregister.
A.MaybeusedasEM_D[31:16]
B.Optionalforhostssupportingmultiplexedaddressanddata.Pullupifnotused.Lowwhenaddressisonthebus.
C.DSPbyteenablesUHPI_HBE[3:2]arenotrequiredinthismode.
D.TwohostaddresslinesorhostGPIOifaddresslinesarenotavailable.
E.A[1],assumingthisaddressincrementsfrom0to1betweentwosuccessive16-bitaccesses.
F.ByteEnables(activeduringreadsandwrites).Someprocessorssupportabyte-enablemodeontheirwrite-enable
pins.
G.Onlyrequiredifneededforstrobetiming.NotrequiredifCSmeetsstrobetimingrequirements.TieUHPI_HDS[2]and
UHPI_HDS[1]opposite.Formoreinformation,seeFigure4-14.
Figure4-15.UHPIMultiplexedHostAddress/DataHalf-WordMode
PeripheralandElectricalSpecifications 56SubmitDocumentationFeedback