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3.12 I2C Prescaler Register (ICPSC)
The I2C prescaler register (ICPSC) is used for dividing down the I2C input clock to obtain the desired
prescaled module clock for the operation of the I2C.
The IPSC bits must be initialized while the I2C is in reset (IRS = 0 in ICMDR). The prescaled frequency
takes effect only when the IRS bit is changed to 1. Changing the IPSC value while IRS = 1 has no effect.
The I2C prescaler register (ICPSC) is shown in Figure 26 and described in Table 19.
Figure 26. I2C Prescaler Register (ICPSC)
31 16
Reserved
R-0
15 8 7 0
Reserved IPSC
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. I2C Prescaler Register (ICPSC) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 These reserved bit locations are always read as zeros. A value written to this field has no effect.
7-0 IPSC 0-FFh I2C prescaler divide-down value. IPSC determines how much the I2C input clock is divided to create the
I2C prescaled module clock:
I2C clock frequency = I2C input clock frequency/(IPSC + 1)
Note: IPSC must be initialized while the I2C is in reset (IRS = 0 in ICMDR).
38
Inter-Integrated Circuit (I2C) Peripheral SPRUEN0D–March 2011
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