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2.11 Reset Considerations
The I2C peripheral has two reset sources: software reset and hardware reset.
2.11.1 Software Reset Considerations
To reset the I2C peripheral, write 0 to the I2C reset (IRS) bit in the I2C mode register (ICMDR). All status
bits in the I2C interrupt status register (ICSTR) are forced to their default values, and the I2C peripheral
remains disabled until IRS is changed to 1. The SDA and SCL pins are in the high-impedance state.
NOTE: If the IRS bit is cleared to 0 during a transfer, this can cause the I2C bus to hang (SDA and
SCL are in the high-impedance state).
2.11.2 Hardware Reset Considerations
When a hardware reset occurs, all the registers of the I2C peripheral are set to their default values and
the I2C peripheral remains disabled until the I2C reset (IRS) bit in the I2C mode register (ICMDR) is
changed to 1.
NOTE: The IRS bit must be cleared to 0 while you configure/reconfigure the I2C peripheral.
Forcing IRS to 0 can be used to save power and to clear error conditions.
2.12 Initialization
Proper I2C initialization is required prior to starting communication with other I2C device(s). Unless a fully
fledged driver is in place, you need to determine the required I2C configuration needed (for example,
Master Receiver, etc.) and configure the I2C controller with the desired settings. Enabling the I2C clock
should be the first task. Then the I2C controller is placed in reset. You now are ready to configure the I2C
controller. Once configuration is done, you need to enable the I2C controller by releasing the controller
from reset. Prior to starting communication, you need to make sure that all status bits are cleared and no
pending interrupts exist. Once the bus is determined to be available (the bus is not busy), the I2C is ready
to proceed with the desired communication.
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Inter-Integrated Circuit (I2C) Peripheral SPRUEN0D–March 2011
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