Filter
Top Products
Block Diagram Descriptions
CSA 803A Service Manual
3Ć29
When the processor requests a hardware timing measurement such as a
propagation delay measurement, the comparator is programmed for the
appropriate measurement level and the transition counter is programmed to
locate the selected transition number and slope. The hardware counts the
strobe pulses that occur from the beginning of the acquisition to the point
where the selected transition occurs. This operation is performed on two
channels Ċ one for each crossing point of the timing measurement. When
the transition points are found, the Acquisition processor reads the sample
number from the hardware and stores it in a specific location in the shared
memory for the Time Base/Controller. The Time Base/Controller reads these
points (from each channel involved in the measurement), subtracts these
points, and then multiplies the result by the sampling interval. The result is a
measurement of the time between the two threshold points.
Timing and Sampling Head Control
This hardware generates analog control voltages that control several samĆ
pling head operating and calibration parameters. For example, the loop gain
calibration adjustment is controlled by an analog voltage generated in the
CSA 803A for each sampling head channel. In addition, three digital control
lines go to each sampling head Ċ two to enable or disable TDR on each
channel and one to enable smoothing for both channels in a head.
This circuit block also generates timing signals that control when waveform
data is digitized and when the measurement hardware is clocked. The time
base sends a strobe pulse to the acquisition system and to the sampling
head to initiate a sample. Each acquisition processor can also generate
strobe pulses locally for SelfĆTests and diagnostic purposes.
Shared RAM
This memory for the A28 Acquisition MPU board contains 16 Kbytes of
shared RAM. This memory is arbitrated on the A25/A28 Acquisition MPU
boards between the Acquisition system processor, the Time Base/Controller
processor, and the A/D converters on the A27 Acquisition Analog board. All
waveform data acquired by the Acquisition system, as well as control and
data messages passed between the Acquisition system and the Time Base/
Controller, pass through this shared memory.
Time Base/Controller Interface
This circuitry handles requests from the Time Base/Controller to access the
shared memory on the A28 Acquisition MPU boards. The shared memory is
then arbitrated and buffered through the Time Base/Controller interface
hardware. This hardware decodes and latches the Time Base/Controller
address and generates a wait signal that holds the Time Base/Controller
processor in a wait state until a bus cycle can be granted to allow the
memory access to complete.
The arbitration logic coordinates requests for access to the shared memory
from the A/D converters, the Acquisition system processor, and the time
base/controller processor.