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Block Diagram Descriptions
Theory of Operation
3Ć24
The A18 Memory Board provides the Executive processor (EXP) with system
RAM (SRAM), NonĆvolatile RAM (NVRAM), and EPROM for most operations.
Support circuitry for the memories and diagnostic circuitry for troubleshootĆ
ing are located onĆboard. All accesses to SRAM, NVRAM, or EPROMs are
initiated by the A17 Executive Processor board (specifically by the EXP or
the DMA controller). Refer to the discussion of the A17 Executive Processor
board, earlier in this section, for bus cycle timing information.
The A18 Memory board consists of the following circuitry:
H Address latches
H Address decode and memory select circuitry
H EPROM and system RAM
H Memory data buffers
H Wait state generator
H Wait state diagnostics
H Memory configuration readback
H NonĆvolatile RAM and battery backup
See Figure 9Ć12 for a block diagram of this board.
Address Latches
This circuitry buffers and holds the address lines for the EPROMs, SRAMs,
NVRAMs, and other onĆboard devices until the end of the bus cycle.
Address Decode and Memory Select
This circuit consists of a programmable array logic (PAL) device that deĆ
codes the address lines to produce five RAM select signals (DCS4Ć8) and
four EPROM select signals (DCS0Ć3). DCS8 enables the SRAM while
DCS4Ć7 enable the NVRAM. All EPROM and RAM select lines are latched,
and the latch outputs are normally enabled. While the latch enable signal is
high, the latch outputs are responsive to changes on the inputs; while the
latch enable signal is low, the select lines are latched.
The EXP on the A17 Executive Processor board generates the address line
inputs, A14ĆA19. Depending upon the position of a jumper on the A17
Executive Processor board, address lines A20ĆA23 can be memory bankĆseĆ
lect lines or microprocessor address lines.
The memory select circuitry provides latched memory select lines and an
enable signal for the memory data buffers.
A18 Memory Board