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Block Diagram Descriptions
CSA 803A Service Manual
3Ć9
The A5 Time Base Controller board consists of the following circuitry:
H Microprocessor (MPU)
H RAM/ROM
H Trigger circuitry
H Time Base circuitry
H Acquisition system interface
H Memory management unit (MMU) interface
See Figure 9Ć5 for the block diagram of this board.
Microprocessor
The microprocessor controls the time base and trigger circuitry in response
to commands from the Executive Processor, performs local onĆline calibraĆ
tion of the time base, schedules waveform acquisitions, and manages the
Acquisition system and waveform data transfers.
RAM/ROM Memory
Both RAM and ROM memory reside within the microprocessor's 1 Mbyte of
address space. The upper 256 Kbytes is reserved as ROM, the lower
128 Kbytes of static RAM is provided for dynamic data storage and local
nonĆvolatile memory. There are 32 Kbytes of memoryĆprovided communicaĆ
tion and waveform storage for the CSA 803A's 8 channels, and another
32 Kbytes for the Strobe Distribution block of the oscilloscope and multiplexĆ
ers. There are 512 Kbytes of memory assigned as communication and
primary waveform storage. Another 32 Kbytes are used to map the commuĆ
nication buffer of the parallel interface with the memory management unit,
and the remaining 32 Kbytes are divided into I/O space and time base
control.
Trigger
This circuitry Is comprised of the trigger recognizer and gated voltage conĆ
trol oscillator. The trigger circuits accept trigger signals from either the Direct
or Prescaler Inputs. The strobe sense signal and internal feedback signals
are used in the SelfĆTests diagnostic process but are not normally used for
data acquisition.
The trigger recognizer sees a valid direct or prescale trigger signal and
outputs this signal to the voltage controlled oscillator that sets the timing for
the strobe signal.
The direct trigger input allows programmed slope and level selection, but
the prescale trigger input is not adjustable.
A5 Time
Base/Controller
Board