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Block Diagrams
Diagrams
9Ć14
Diagnostic
Clocks
Data
Buffer
Address
Decode/
Select
Latch
Address
Latch
I/O
Delayed
Data
Buffer
Timer
Configuration
Logic
Clock
Generator
Temp/Tone
Readback
Buffer
Timer
Real
Time
Clock
SDI
Tone
Generator
Data
Buffer
Address
Buffer
Control
Buffer
Data
Buffer
Control
Buffer
I/O Data Bus
Control
J78
to Rear
Panel
J72
to Fron
t
Panel
Control
Control
J72
P105
Executive
Data Bus
Address
Buffer
Figure 9Ć9:ăA14 I/O Board Block Diagram
Display IC
Microprocessor
Bit Map
RAM
SYNC
Display
MMU IC
EXP
Interface
Interface
Time Base/
Controller
Interface
Waveform
RAM
To/From
A5
Time Base/Controller
To/From
A17
Executive
Processor
Waveform
Display
RAM
Video
DAC
VIDEO
Figure 9Ć10:ăA15 MMU Board Block Diagram