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Block Diagrams
Diagrams
9Ć18
Signal
Offset DAC
Sampling
Head
Inputs
+2V CAL
-2VCAL
+16mV CAL
Input
Multiplexer
Input Buffer
14 Bit -2.1V to +2.1V 12 Bit 0V to +3V
Variable
Gain DAC
+
X2/X20
X2/X20
Gain
x
+
Vin
+1V REF
-1V REF
Vrt
Vrb
Vrm
Multiplier
x0.5 to x5
Transition
Logic
Comparator
+
-
Comparator
Level DAC
16-Bit DOT
Number
-1V to +1V
O V Center Scale
Offset
Correction
DAC
8-Bit
-500mV to +500mV
14-Bit
-2.1V to +2.1V
A/D
Converter
Figure 9Ć15:ăA27 Acquisition Analog Board Block Diagram
Sampling
Head
Control
Filter and
Transition
Counter
Shared
Triple
Port
RAM
Time Base/
Controller
Interface
ROM
Microprocessor
Filter and
Transition
Counter
To A/D
Converter
To/From
Time Base
Controller
To A/D
Converter
From Comparator
Channel A
From Comparator
Channel B
Figure 9Ć16:ăA28 Acquisition MPU Board Block Diagram