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20 Agilent N5161A/62A/81A/82A/83A MXG Signal Generators User’s Guide
Signal Generator Overview Preliminary
Rear Panel Overview – N5161A/62A
1
/81A/82A MXG Preliminar
AUX I/O
View looking into rear panel female 50–pin
25
1
2650
Pin 1 = Event 1
Pin 2 = Event 2
Pin 3 = Event 3
Pin 4 = Event 4
Pin 5 = Sample Rate Clock Out
Pin 6 = Patt Trig 2
Pins 7–25 = Reserved*
Pins 26–50 = Ground
*Future Capability
Event 1, 2, 3, and 4 (pins 1 − 4)
A pulse that can be used to trigger the start of a data pattern, frame, or timeslot.
Adjustable to ± one timeslot; resolution = one bit
Markers
Each Arb–based waveform point has a marker on/off condition associated with it.
Marker level = +3.3 V CMOS high (positive polarity selected); –3.3 V CMOS low (negative polarity
selected).
Patt Trig 2 (pin 6)
A TTL/CMOS low to TTL/CMOS high, or TTL/CMOS high to TTL/CMOS low edge trigger.
The input to this connector triggers the internal digital modulation pattern generator to start a single pattern output or to stop and
re–synchronize a pattern that is being continuously output.
To synchronize the trigger with the data bit clock, the trigger edge is latched, then sampled during the falling edge of the internal data bit
clock.
This is an external trigger for all ARB waveform generator triggers. Minimum pulse width = 100 ns. Damage levels: < −0.5 and > +5.5 V.
Sample Rate Clock Out (pin 5)
This output is used with an internal baseband generator. This pin relays a CMOS bit clock signal for synchronizing serial data.
Damage levels:< −0.5 and > +5.5 V.
The AUX I/O connector is a shielded .050 series board mount connector.