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1-3 M32R-FPU Software Manual (Rev.1.01)
CRn
b31
b0
CPU PROGRAMMING MODEL
1.3 Control Registers
1.3 Control Registers
There are 6 control registers which are the Processor Status Word Register (PSW),
the Condition Bit Register (CBR), the Interrupt Stack Pointer (SPI), the User Stack
Pointer (SPU), the Backup PC (BPC) and the Floating-point Status Register (FPSR).
The dedicated MVTC and MVFC instructions are used for writing and reading these
control registers.
In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW
instruction or the CLRPSW instruction.
Figure 1.3.1 Control Registers
Backup PC
Floating-point Status Register
BPC
CR6
CR0
CR1
CR2
CR3
Processor Status Register
Condition Bit Register
Interrupt Stack Pointer
User Stack Pointer
Notes: • CRn (n = 0 - 3, 6 and 7) denotes the control register number.
• The dedicated MVTC and MVFC instructions are used for writing and reading these control registers.
• The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW instruction or the CLRPSW
instruction.
PSW
CBR
SPI
SPU
FPSR
CR7