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APPENDICES
APPENDICES-4
M32R-FPU Software Manual (Rev.1.01)
mnemonic function condition bit (C)
ADD Rdest,Rsrc Rdest = Rdest + Rsrc –
ADD3 Rdest,Rsrc,#imm16 Rdest = Rsrc + (sh)imm16 –
ADDI Rdest,#imm8 Rdest = Rdest + (sb)imm8 –
ADDV Rdest,Rsrc Rdest = Rdest + Rsrc change
ADDV3 Rdest,Rsrc,#imm16 Rdest = Rsrc + (sh)imm16 change
ADDX Rdest,Rsrc Rdest = Rdest + Rsrc + C change
AND Rdest,Rsrc Rdest = Rdest & Rsrc –
AND3 Rdest,Rsrc,#imm16 Rdest = Rsrc & (uh)imm16 –
BC pcdisp8 if(C) PC=PC+((sb)pcdisp8<<2) –
BC pcdisp24 if(C) PC=PC+((s24)pcdisp24<<2) –
BCLR #bitpos,@(disp16,Rsrc) *(sb *)(Rsrc + (sh)disp16) & = ~(1<<(7-bitpos)) –
BEQ Rsrc1,Rsrc2,pcdisp16 if(Rsrc1 == Rsrc2) PC=PC+((sh)pcdisp16<<2) –
BEQZ Rsrc,pcdisp16 if(Rsrc == 0) PC=PC+((sh)pcdisp16<<2) –
BGEZ Rsrc,pcdisp16 if(Rsrc >= 0) PC=PC+((sh)pcdisp16<<2) –
BGTZ Rsrc,pcdisp16 if(Rsrc > 0) PC=PC+((sh)pcdisp16<<2) –
BL pcdisp8 R14=PC+4,PC=PC+((sb)pcdisp8<<2) –
BL pcdisp24 R14=PC+4,PC=PC+((s24)pcdisp24<<2) –
BLEZ Rsrc,pcdisp16 if(Rsrc <= 0) PC=PC+((sh)pcdisp16<<2) –
BLTZ Rsrc,pcdisp16 if(Rsrc < 0) PC=PC+((sh)pcdisp16<<2) –
BNC pcdisp8 if(!C) PC=PC+((sb)pcdisp8<<2) –
BNC pcdisp24 if(!C) PC=PC+((s24)pcdisp24<<2) –
BNE Rsrc1,Rsrc2,pcdisp16 if(Rsrc1 != Rsrc2) PC=PC+((sh)pcdisp16<<2) –
BNEZ Rsrc,pcdisp16 if(Rsrc != 0) PC=PC+((sh)pcdisp16<<2) –
BRA pcdisp8 PC=PC+((sb)pcdisp8<<2) –
BRA pcdisp24 PC=PC+((s24)pcdisp24<<2) –
BSET #bitpos,@(disp16,Rsrc) *(sb *)(Rsrc + (sh)disp16) | = (1<<(7-bitpos)) –
BTST #bitpos,Rsrc (Rsrc>>(7-bitpos))&1 change
CLRPSW #imm8 PSW & = ~imm8 | 0xffffff00 change
CMP Rsrc1,Rsrc2 (s)Rsrc1 < (s)Rsrc2 change
CMPI Rsrc,#imm16 (s)Rsrc < (sh)imm16 change
CMPU Rsrc1,Rsrc2 (u)Rsrc1 < (u)Rsrc2 change
CMPUI Rsrc,#imm16 (u)Rsrc < (u)((sh)imm16) change
DIV Rdest,Rsrc Rdest = (s)Rdest / (s)Rsrc –
DIVU Rdest,Rsrc Rdest = (u)Rdest / (u)Rsrc –
FADD Rdest,Rsrc1,Rsrc2 Rdest = Rsrc1 + Rsrc2 –
FCMP Rdest,Rsrc1,Rsrc2 Rdest = (Rsrc1 == Rsrc2)?32'h00000000:((Rsrc1< –
Rsrc2)?{1.31'bx}:{0.31'bx}
FCMPE Rdest,Rsrc1,Rsrc2 FCMP with Exception when unordered –
FDIV Rdest,Rsrc1,Rsrc2 Rdest = Rsrc1 / Rsrc2 –
Appendix 2 Instruction List
The M32R-FPU instruction list is shown below (in alphabetical order).
APPENDIX 2
Appendix 2 Instruction List