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APPENDICES
APPENDICES-11 M32R-FPU Software Manual (Rev.1.01)
Appendix Figure 3.2.2 Pipeline Flow with no Stall (2)
<Case 4> Three FPU instructions continue consecutively with no register dependency
IF D E1 WB
FADD R0,R5,R6
FSUB R1,R6,R7
IF D
E2
E1 WBE2
E1 WBE2
E1 WBE2
IF D
FMUL R2,R7,R8
FCMP R0,R0,R3
IF D
IF D EA WB
FMADD R0,R5,R6
FMADD R1,R6,R7
IF D
EM E2
EA WBEM E2
EA WBEM E2
EA WBEM E2
IF D
FMADD R2,R7,R8
FMADD R3,R80,R9
IF D
<Case 5> Four FMADD or FMSUB instructions continue consecutively with no register dependency
* The FDIV instruction takes 14 cycles in E1 stage.
APPENDIX 3
Appendix 3 Pipeline Processing