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APPENDICES
APPENDICES-26
M32R-FPU Software Manual (Rev.1.01)
APPENDIX 6
Appendix 6 M32R-FPU Specification Supplemental Explanation
(3) When Invalid Operation Exception occurs in Step 1
■ If at least one of [R1, R2] is an SNaN
<When EV = 0: IVLD occurs>
Type of R0 Condition FMUL + FADD Operation FMADD Operation
Normalized – R0 = R3 Same as left
(SNaN converted to QNaN)
Denormalized DN=0 R0 = R3 Same as left
number (SNaN converted to QNaN)
DN=1 R0 = R3 Same as left
(SNaN converted to QNaN)
QNaN – R0 = maintained (QNaN) Same as left
SNaN – R0 = R0 converted to QNaN Same as left
<When EV = 1: IVLD occurs>
Type of R0 Condition FMUL + FADD Operation FMADD Operation
Normalized – EIT occurs when FMUL is EIT occurs,
number, 0, completed R0 = maintained
Infinity R0 = maintained
Denormalized DN=0 Same as above UIPL occurs,
number EIT occurs
R0 = maintained
DN=1 Same as above EIT occurs,
R0 = maintained
QNaN – Same as above Same as above
SNaN – Same as above Same as above
■ If “✕ ∞” occurs in [R1, R2]
<When EV = 0: IVLD occurs>
Type of R0 Condition FMUL + FADD Operation FMADD Operation
Normalized – R0 = H'7FFF FFFF Same as left
Denormalized DN=0 R0 = H'7FFF FFFF Same as left
number DN=1 R0 = H'7FFF FFFF Same as left
QNaN – R0 = maintained (QNaN) Same as left
SNaN – R0 = R0 converted to QNaN Same as left
<When EV = 1: IVLD occurs>
Same results as when “If at least one of [R1, R2] is an SNaN.”