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APPENDICES
APPENDICES-13 M32R-FPU Software Manual (Rev.1.01)
Appendix Figure 3.2.4 Pipeline Flow with Stalls (2)
<Case 3> A branch instruction is executed (except for the case in which no branch occurs
at a conditional branch instruction)
IF D E WB
Branch Instruction
IF D WBE
IF D WBEstall stall
stall
IF D WBEstall
IF D
Bypass process
branch instruction is executed
stall stall
<Case 4> The subsequent instruction uses an operand read from the memory
IF D E WB
LD
R1
,@R2
IF D WB
MEM2MEM1
ADD R3,
R1
stall stall
IF
Bypass process
IF D E WB
LD
R1
,@R2
IF D WB
MEM2MEM1
IF D E
ADD R4,R5
WB
ADD R3,
R1
stall
Bypass process
IF D E WB
LD
R1
,@R2
IF EMDE2WBEA
MEM2MEM1
IF D E
ADD R4,R5
WB
FMADD
R1
,R6,R7
Bypass process
IF D E WB
LD
R1
,@R2
IF D WBE
MEM2MEM1
IF D E
ADD R4,R5
WB
IF D E
ADD R6,R7
WB
ADD R3,
R1
E
E
APPENDIX 3
Appendix 3 Pipeline Processing