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7−1
7 Microcontroller Operation
The TAS3002 device contains an internal microcontroller programmed by Texas Instruments to perform
housekeeping and interface functions. Additionally, it handles I
2
C communication and general purpose input
functions.
7.1 General Description
The microcontroller uses a 256f
S
system clock and can access up to 8K bytes of memory. It interfaces with the digital
audio interface I
2
C master/slave for downloading data and coefficients. It also interfaces with two internal DSPs for
transferring coefficients and other information.
The TAS3002 coefficients are loaded through I
2
C in the master or slave mode. Standard audio processing functions
(volume, bass, and treble) can be controlled/activated through external switches connected to the six GPI terminals.
Upon reset, the internal microcontroller sets all coefficients and audio parameters to the default values. See
Section 7.2.2 for default values.
If the TAS3002 address is 68h (ADDR_SEL=0), it becomes the bus master device and attempts to load parameters
and coefficients from the external EEPROM. If no EEPROM is present, the TAS3002 device remains in its default
condition. If addresses other than 68h/69h are set, the TAS3002 device only operates as an I
2
C slave device.
If the microcontroller determines the TAS3002 device has an I
2
C address of 68h/69h and the EEPROM is present,
the microcontroller downloads coefficients from the EEPROM. Once the download is complete, it enables the serial
audio in the mode defined by an I
2
C write to the MCR to transfer data into and out of the device. Before reading the
EEPROM, the serial audio port defaults to I
2
S mode.
The TAS3002 device allows the user to update volume, bass, and treble dynamically by an I
2
C slave command or
by a simple GPI input. The GPI can select volume up and down, bass/treble up and down, or digital equalizations.
Up to five different equalizations (that is, flat, jazz, rock, voice, etc.) can be stored in the external EEPROM. Also,
DRCE, MCR1, MCR2, and loudness contour are enabled and disabled by I
2
C.
When the TAS3002 device operates in the I
2
C master mode, it echoes changes to all of its functions to other I
2
C
addresses that are defined in its external EEPROM. If no addresses are defined, it does not echo.
7.2 Power-Up/Power-Down Reset
7.2.1 Power-Up Sequence
An active low on terminal 6 (RESET) while MCLK is running resets the internal microcontroller and DSPs. RESET
synchronizes internally and can be asserted asynchronously or with the simple RC circuit in Figure 7−1. On reset,
SCL and SDA go to a high-impedance state. If the I
2
C address is set to 68h, approximately 400 µs after RESET
returns to a 1, the device sends a one-byte query via I
2
C to look for an EEPROM. If an EEPROM is found, the TAS3002
becomes an I
2
C master; otherwise, it becomes an I
2
C slave. When using address 68h in the slave mode, an external
master must wait until after the EEPROM query or else bus contention and improper operation occur.
I
2
C address x6Ah does not query the bus for an EEPROM. The address for the EEPROM is A0h.
7.2.2 Reset
The TAS3002 device has an asynchronous reset terminal (RESET). This reset is synchronized with various clocks
used in this device to generate a synchronous internal reset. Upon reset, the TAS3002 device goes through the
following process:
• Clears all the RAM memory content