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SPRS230L–OCTOBER 2003–REVISED DECEMBER 2009
The SPI port operation is configured and controlled by the registers listed in Table 4-10 through
Table 4-13.
Table 4-10. SPI-A Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
(1)
SPICCR 0x7040 1 SPI-A Configuration Control Register
SPICTL 0x7041 1 SPI-A Operation Control Register
SPISTS 0x7042 1 SPI-A Status Register
SPIBRR 0x7044 1 SPI-A Baud Rate Register
SPIRXEMU 0x7046 1 SPI-A Receive Emulation Buffer Register
SPIRXBUF 0x7047 1 SPI-A Serial Input Buffer Register
SPITXBUF 0x7048 1 SPI-A Serial Output Buffer Register
SPIDAT 0x7049 1 SPI-A Serial Data Register
SPIFFTX 0x704A 1 SPI-A FIFO Transmit Register
SPIFFRX 0x704B 1 SPI-A FIFO Receive Register
SPIFFCT 0x704C 1 SPI-A FIFO Control Register
SPIPRI 0x704F 1 SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 4-11. SPI-B Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
(1)
SPICCR 0x7740 1 SPI-B Configuration Control Register
SPICTL 0x7741 1 SPI-B Operation Control Register
SPISTS 0x7742 1 SPI-B Status Register
SPIBRR 0x7744 1 SPI-B Baud Rate Register
SPIRXEMU 0x7746 1 SPI-B Receive Emulation Buffer Register
SPIRXBUF 0x7747 1 SPI-B Serial Input Buffer Register
SPITXBUF 0x7748 1 SPI-B Serial Output Buffer Register
SPIDAT 0x7749 1 SPI-B Serial Data Register
SPIFFTX 0x774A 1 SPI-B FIFO Transmit Register
SPIFFRX 0x774B 1 SPI-B FIFO Receive Register
SPIFFCT 0x774C 1 SPI-B FIFO Control Register
SPIPRI 0x774F 1 SPI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Copyright © 2003–2009, Texas Instruments Incorporated Peripherals 77
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