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SPRS230L–OCTOBER 2003–REVISED DECEMBER 2009
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6.6.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 280x DSPs. Table 6-6 and Table 6-7 list the cycle times of various clocks.
Table 6-6. TMS320x280x Clock Table and Nomenclature (100-MHz Devices)
MIN NOM MAX UNIT
t
c(OSC)
, Cycle time 28.6 50 ns
On-chip oscillator
clock
Frequency 20 35 MHz
t
c(CI)
, Cycle time 10 250 ns
XCLKIN
(1)
Frequency 4 100 MHz
t
c(SCO)
, Cycle time 10 500 ns
SYSCLKOUT
Frequency 2 100 MHz
t
c(XCO)
, Cycle time 10 2000 ns
XCLKOUT
Frequency 0.5 100 MHz
t
c(HCO)
, Cycle time 10 20
(3)
ns
HSPCLK
(2)
Frequency 50
(3)
100 MHz
t
c(LCO)
, Cycle time 10 40
(3)
ns
LSPCLK
(2)
Frequency 25
(3)
100 MHz
t
c(ADCCLK)
, Cycle time (All devices except F2809) 80 ns
Frequency (All devices except F2809) 12.5 MHz
ADC clock
t
c(ADCCLK)
, Cycle time (F2809) 40 ns
Frequency (F2809) 25 MHz
(1) This also applies to the X1 pin if a 1.8-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default reset value if SYSCLKOUT = 100 MHz.
Table 6-7. TMS320x280x/2801x Clock Table and Nomenclature (60-MHz Devices)
MIN NOM MAX UNIT
t
c(OSC)
, Cycle time 28.6 50 ns
On-chip oscillator
clock
Frequency 20 35 MHz
t
c(CI)
, Cycle time 16.67 250 ns
XCLKIN
(1)
Frequency 4 60 MHz
t
c(SCO)
, Cycle time 16.67 500 ns
SYSCLKOUT
Frequency 2 60 MHz
t
c(XCO)
, Cycle time 16.67 2000 ns
XCLKOUT
Frequency 0.5 60 MHz
t
c(HCO)
, Cycle time 16.67 33.3
(3)
ns
HSPCLK
(2)
Frequency 30
(3)
60 MHz
t
c(LCO)
, Cycle time 16.67 66.7
(3)
ns
LSPCLK
(2)
Frequency 15
(3)
60 MHz
t
c(ADCCLK)
, Cycle time 133.33 ns
ADC clock
Frequency 7.5 MHz
(1) This also applies to the X1 pin if a 1.8-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default reset value if SYSCLKOUT = 60 MHz.
104 Electrical Specifications Copyright © 2003–2009, Texas Instruments Incorporated
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