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SPRS230L–OCTOBER 2003–REVISED DECEMBER 2009
Signal Descriptions (continued)
PIN NO.
GGM/
NAME DESCRIPTION
(1)
PZ
ZGM
PIN #
BALL #
V
DD
10 E2
V
DD
42 G6
V
DD
59 F10
CPU and Logic Digital Power Pins (1.8 V)
V
DD
68 D7
V
DD
85 B6
V
DD
93 D4
V
DDIO
3 C2
V
DDIO
46 H7
Digital I/O Power Pin (3.3 V)
V
DDIO
65 E9
V
DDIO
82 A7
V
SS
2 B1
V
SS
11 E3
V
SS
41 H6
V
SS
49 K9
V
SS
55 H10
V
SS
62 F7 Digital Ground Pins
V
SS
69 D10
V
SS
77 A9
V
SS
87 D6
V
SS
89 A5
V
SS
94 A4
GPIOA AND PERIPHERAL SIGNALS
(2) (3)
GPIO0 General purpose input/output 0 (I/O/Z)
(4)
EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)
47 K8
- -
- -
GPIO1 General purpose input/output 1 (I/O/Z)
(4)
EPWM1B Enhanced PWM1 Output B (O)
44 K7
SPISIMOD SPI-D slave in, master out (I/O) (not available on 2801, 2802)
- -
GPIO2 General purpose input/output 2 (I/O/Z)
(4)
EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)
45 J7
- -
- -
GPIO3 General purpose input/output 3 (I/O/Z)
(4)
EPWM2B Enhanced PWM2 Output B (O)
48 J8
SPISOMID SPI-D slave out, master in (I/O) (not available on 2801, 2802)
- -
GPIO4 General purpose input/output 4 (I/O/Z)
(4)
EPWM3A Enhanced PWM3 output A and HRPWM channel (O)
51 J9
- -
- -
GPIO5 General purpose input/output 5 (I/O/Z)
(4)
EPWM3B Enhanced PWM3 output B (O)
53 H9
SPICLKD SPI-D clock (I/O) (not available on 2801, 2802)
ECAP1 Enhanced capture input/output 1 (I/O)
(2) Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2 for details.
(3) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.
(4) The pullups on GPIO0-GPIO11 pins are not enabled at reset.
Copyright © 2003–2009, Texas Instruments Incorporated Introduction 21
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TMS320C2801 TMS320F28016 TMS320F28015