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SPRS230L–OCTOBER 2003–REVISED DECEMBER 2009
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8 Revision History
This data sheet revision history highlights the technical changes made to the SPRS230K device-specific
data sheet to make it an SPRS230L revision.
Scope: Changed MIN N
f
value [Flash endurance for the array (write/erase cycles)] from 100 cycles to
20000 cycles. See Table 6-43 and Table 6-44.
Changed TYP N
f
value [Flash endurance for the array (write/erase cycles)] from 1000 cycles to
50000 cycles. See Table 6-43 and Table 6-44.
See table below.
LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS
Table 2-3 Signal Descriptions:
• TRST: Changed "In a low-noise environment, TRST may be left floating. In other instances, an external
pulldown resistor is highly recommended" to "An external pulldown resistor is required on this pin"
Figure 4-4 ePWM Sub-Modules Showing Critical Internal Signal Interconnections:
• Changed TBCTL[CNTLDE] to TBCTL[PHSEN]
• Resized "HiRes PWM (HRPWM)" dashed box
Table 4-5 ADC Registers:
• 0x711E–0x711F: Changed DESCRIPTION from "ADC Status Register" to "Reserved"
Section 5.2 Documentation Support:
• Updated Software list
Table 6-37 SPI Slave Mode External Timing (Clock Phase = 1):
• Parameter 18 (Valid time, SPISOMI data valid after SPICLK low): Changed "(clock polarity = 0)" to "(clock
polarity = 1)"
• Parameter 18 (Valid time, SPISOMI data valid after SPICLK high): Changed "(clock polarity = 1)" to "(clock
polarity = 0)"
Table 6-43 Flash Endurance for A and S Temperature Material:
• N
f
[Flash endurance for the array (write/erase cycles)]:
– Changed MIN value from 100 cycles to 20000 cycles
– Changed TYP value from 1000 cycles to 50000 cycles
Table 6-44 Flash Endurance for Q Temperature Material:
• N
f
[Flash endurance for the array (write/erase cycles)]:
– Changed MIN value from 100 cycles to 20000 cycles
– Changed TYP value from 1000 cycles to 50000 cycles
134 Revision History Copyright © 2003–2009, Texas Instruments Incorporated
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