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YMF715E
May 21, 1997
-46-
AC Characteristics
CPU Interface & DMA BUS Cycle :Fig.1,2,3,4,5,6,7,8
Note : DV
SS
=AV
SS
=0[V], T
OP
=0~70 , DV
DD
=5.0 0.25[V] or 3.3 0.30[V], AV
DD
=5.0[V]
*... The value into the brackets is specified at DV
DD
=3.3 0.30[V].
Serial Audio (Zoomed Video) Interface Input :Fig.9
Note : DV
SS
=AV
SS
=0[V], T
OP
=0~70 , DV
DD
=5.0 0.25[V] or 3.3 0.30[V], AV
DD
=5.0[V]
Duty Search Point is 1/2 DV
DD
.
Item Symbol Min. Typ. Max. Unit
/DACK inactive to /IOW, /IOR falling edge t
AKS
50 ns
/DACK active from /IOW, /IOR rising edge t
AKH
10 ns
Address set up to /IOW, /IOR active t
AS
40 ns
Address hold to /IOW, /IOR inactive t
AH
10 ns
/IOW Write Pulse Width t
WW
90 ns
Write Data set up to /IOW active t
WDS
20 ns
Write Data hold to /IOW inactive t
WDH
10 ns
/IOR Read Pulse Width t
RW
90 ns
Read Data access time t
ACC
80 ns
Read Data hold from /IOR inactive t
RDH
0ns
DRQ hold from /IOW, /IOR falling edge t
DGH
020ns
/DACK set up to /IOW, /IOR falling edge t
SF
25 ns
/DACK hold to /IOW, /IOR rising edge t
HR
25 ns
Time between rising edge of /IOW, /IOR to next
falling edge of /IOW, /IOR
t
NX
100 ns
Valid Address from /SYNCS or /MCS or /CDCS1-0 t
EX1
70(90) * ns
/SYNCS or /MCS or /CDCS1-0 hold to Valid Address
t
EX2
70(90) * ns
RESET Pulse Width t
RST
90 s
Item Symbol Condition Min. Typ. Max. Unit
BCLK Cycle f
BCK
32fs 48fs 64fs kHz
BCLK Duty D
BCLK
40 50 60 %
LRCK Hold Time t
LRH
BCLK /LRCK
-120 120 ns
SIN Set up Time t
DS
BCLK /SIN
20 ns
SIN Hold Time t
DH
BCLK /SIN
20 ns
CLKO Frequency f
CLKO33
33.8688 MHz
CLKO Duty D
CLKO33
f
33
=50% 40 50 60 %