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YMF715E
May 21, 1997
-34-
Interrupt Channel configuration (R/W):
Index D7 D6 D5 D4 D3 D2 D1 D0
IRQ-B IRQ-A
OPL3 MPU SB WSS OPL3 MPU SB WSS
There are four devices (WSS (Windows Sound System CODEC), SB (Sound Blaster
compatible portion), OPL3, MPU (MPU401)) that can be an interrupt source. This
register specifies what interrupt source is routed to two physical interrupt (IRQA and
IRQB) of OPL3-SA3. The device written to ”1” is assigned to the corresponding interrupt.
And by writing all “1” to upper or lower half byte, it is possible to share all interrupt
sources to a single physical interrupt line.
default : 69h
IRQ-A: WSS + OPL3
IRQ-B: SB + MPU401
Notice)
Do not assign a device to both IRQA and IRQB.
Interrupt (IRQ-A) status (RO):
Index D7 D6 D5 D4 D3 D2 D1 D0
04h - MV OPL3 MPU SB TI CI PI
This register is the status register that indicates which is the interrupt source of IRQA.
When an interrupt occurs, the corresponding bit becomes “1” and its flag (except MV bit)
is cleared when the interrupt routine is completed. This register is not cleared by writing
to this register.
MV... Hardware Volume Interrupt Flag : If configured VEN=1(index 0Ah, D7
bit), the interrupt occurs when either /VOLUP or /VOLDW is low level or
when both are low level to request mute. The interrupt will be posted in
the IRQ-A channel, if IRQ-A MV=1 (index 17h, D4 bit).
Note that when the muting is in effect, the subsequent mute requests which
does not change any register contents will generate interrrupts. The
ignored UP/DOWN requests (UP requests with 0dB Volume attn.,
DOWN requests with -30dB) will not generate interrupts.
This bit is cleared upon host's reading the Master Volume Lch register at
index 07h.
OPL3... Internal FM-synthesizer Timer Flag : Note that this flag will become
undefined for the configurations (SEL=3,4,7) using external synthesizer
(i.e. OPL4-ML/ML2).
MPU... MPU401 Interrupt Flag
SB... Sound Blaster compatible Playback Interrupt Flag
TI... Timer Flag of CODEC
CI... Recording Flag of CODEC
PI... Playback Flag of CODEC