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TX FIFO _0
LSPCLK
WUT
Frame Format and Mode
Even/Odd Enable
Parity
SCI RX Interrupt select logic
BRKDT
RXRDY
SCIRXST.6
SCICTL1.3
8
SCICTL2.1
RX/BK INT ENA
SCIRXD
SCIRXST.1
TXENA
SCI TX Interrupt select logic
TX EMPTY
TXRDY
SCICTL2.0
TX INT ENA
SCITXD
RXENA
SCIRXD
RXWAKE
SCICTL1.6
RX ERR INT ENA
TXWAKE
SCITXD
SCICCR.6 SCICCR.5
SCITXBUF.7-0
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 - 0
Transmitter-Data
Buffer Register
8
SCICTL2.6
SCICTL2.7
Baud Rate
LSbyte
Register
RXSHF
Register
TXSHF
Register
SCIRXST.5
1
TX FIFO _1
-----
TX FIFO _15
8
TX FIFO registers
TX FIFO
TX Interrupt
Logic
TXINT
SCIFFTX.14
RX FIFO _15
SCIRXBUF.7-0
Receive Data
Buffer register
SCIRXBUF.7-0
-----
RX FIFO_1
RX FIFO _0
8
RX FIFO registers
SCICTL1.0
RX Interrupt
Logic
RXINT
RX FIFO
SCIFFRX.15
RXFFOVF
RX Error
SCIRXST.7
PEFE OE
RX Error
SCIRXST.4 - 2
To CPU
To CPU
AutoBaud Detect logic
SCICTL1.1
SCIFFENA
Interrupts
Interrupts
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
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SPRS230L–OCTOBER 2003–REVISED DECEMBER 2009
Figure 4-13 shows the SCI module block diagram.
Figure 4-13. Serial Communications Interface (SCI) Module Block Diagram
Copyright © 2003–2009, Texas Instruments Incorporated Peripherals 75
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Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015