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MZ-R900
2828
6-2. BLOCK DIAGRAM – AUDIO Section –
VC B+
F801
F
RMC KEY
RVDD
DTCK
CDWM 2V
CDWM DATA
KEY-R
RGND
(LINE IN JACK)
OPTICAL
RECEIVER
J302
i/LINE OUT
J301
LINE IN
(OPT)
J303
MIC
(PLUG IN POWER)
• SIGNAL PATH
: PLAYBACK
: REC (ANALOG IN)
: REC (DIGITAL IN)
2
1113
5
4
16
10
9
12
13
3
1
14 15 16
183 186 178
AOUT
SEL
143
142
144
145
192215 191 2 193
5
7
4
6
2
3
27
1
26
28
19
71
25
6970
25
23
22
21
20
17
16
15
179
180
181
1
219
234
B+ SWITCH
Q302
VIF B+
REGULATOR
MUTING
MIC AMP
IC303
IN2
IN1
STBY
GV
OUT1
OUT2
HP/LINE
SWITCH
GAIN
AMP
GAIN
AMP
CLOCK
DIVIDER
D/A
CONVERTER
AUDIO
I/F
CONTROL
CONTROL
REGISTER
I/F
A/D
CONVERTER
&
HPF
HEADPNONE AMP
IC302
LOUT
ROUT
GA-L
GA-R
L-IN
R-IN
HP/L
MUTE
BEEP
210
TSB SLAVE
DETECT
Q803
BEEP
XMUTE
XJAC DET
XOPT CTL
FS256
LRCK
XBCK
OSCO
OSCI
XCS NV
SDIO
SCK0
SDO0
OPT DET
MIC SENSE
XMIC DET
TSB SLV VDD
RMC DTCK
TSB SLVI
TSB SLVO
TSB SLV CHK
SYSTEM CONTROLLER,
DIGITAL SIGNAL PROCESSOR
16M BIT D-RAM
IC801 (2/3)
RIN1
RIN2
LIN1
LIN2
A/D, D/A
CONVERTER
IC301
LOUT2
ROUT2
OPGAL
OPGAR
24
X801
45.1584MHz
SIO
SO0
SCK0
SDI0
SDO0
SCK0
SCK0
SDO0
DADT
ADDT
DIN1
SDO0, SDI0, SCK0
XCS
SK
DI
DO
LOUT1
ROUT2
MCLK
SDTO
SDTI
BCLK
CCLK
CSN
SSB
LRCK
CDTI
B
A
C
G
EEPROM
IC804
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