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Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21
36
NOTES:
1. INTRN or OP3-OP7 when used as interrupt outputs.
2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
signal, V
M
, to a point 0.5V above V
OL
. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and
test environment are pronounced and can greatly affect the resultant measurement.
V
M
V
OL
+0.5V
V
OL
WRN
INTERRUPT
1
OUTPUT
t
IR
V
M
V
OL
+0.5V
V
OL
RDN
INTERRUPT
1
OUTPUT
t
IR
SD00136
Figure 10. Interrupt Timing (80xxx mode)
C1 = C2 ∼ 24pF FOR C
L
= 20pF
t
CLK
t
CTC
t
Rx
t
Tx
X1/CLK
CTCLK
RxC
TxC
t
CLK
t
CTC
t
Rx
t
Tx
V
CC
470Ω
X1
X2*
CLK
*NOTE: X2 MUST BE LEFT OPEN.
X2
3.6864MHz
X1
C1
C2
SC28L91
NOTE:
RESISTOR REQUIRED
FOR TTL INPUT.
TO UART
CIRCUIT
50kΩ
to
100kΩ
3pF
3pF
C1 and C2 should be chosen according to the crystal manufacturer’s specification.
C1 and C2 values will include any parasitic capacitance of the wiring and X1 X2 pins.
Gain at 3.6864MHz: 9 to 13 dB
2pF
4pF
Package capacitance approximately 4pF.
SD00704
PARASITIC CAPACITANCE
PARASITIC CAPACITANCE
Figure 11. Clock Timing