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Philips Semiconductors Product data sheet
SC28L91
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
2004 Oct 21
34
X1/CLK
A1–A4
RWN
CSN
D0–D7
DTACKN
t
CSC
t
AS
t
CS
t
DF
t
DAT
t
DAH
t
CH
t
RWD
t
DD
t
DCR
t
AH
DATA VALID
NOT
VALID
t
DA
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.
SD00687
Figure 6. Bus Timing (Read Cycle) (68XXX mode)
X1/CLK
A1–A4
RWN
CSN
D0–D7
DTACKN
t
CSC
t
AS
t
CS
t
DH
t
DAT
t
DAH
t
CH
t
RWD
t
DS
t
DCW
t
AH
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.
SD00688
Figure 7. Bus Timing (Write Cycle) (68XXX mode)
NOTE:
For Figures 6 and 7 WRN changing within the time of CEN low may cause short read or write pulses that could upset internal pointers and
registers. Bus action terminates on the rise of CEN or the fall of DACKN, which ever occurs first.