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3131
MZ-B100
6-3. BLOCK DIAGRAM – MAIN Section (2/3) –
VC B+
F301
F
RMC KEY
RVCC
DTCK
KEY-R
RGND
(LINE IN JACK)
OPTICAL
RECEIVER
J301
LINE IN
(OPT)
J303
MIC
(PLUG IN POWER)
• R-CH is omitted
• SIGNAL PATH
: PLAYBACK
: REC (ANALOG IN)
: REC (DIGITAL IN)
2
24
4
23
22
12
13
21
2
3
1
5
7
15
5 4
17 16
183 218 240
143
142
144
145
192215 191 1 193
25
70
179
180
181
1
219
234
B+ SWITCH
Q301
VIF B+
MUTING
POWER
SWITCH
HEADPNONE AMP
IC302
OUT_L
OUT R
OUT B BEEP
OUT A BEEP
IN_L
IN_R
HP/L
MUTE
BEEP
210
BEEP
MUTE
XHP_STBY
XJAC_DET
XOPT_CTL
XBCK
OSCO
OSCI
XCS_NV
SDIO
SCK0
SDO0
OPT_DET
MICAMP_CTL
XMIC_DET
XMONO_MODE
SP_AMP
TSB_SLV_VDD
RMC_DTCK
TSB_SLVI
TSB_SLVO
TSB_SLV_CHK
SYSTEM CONTROL,
DIGITAL SIGNAL PROCESSOR
16M D-RAM
IC801 (2/3)
24
X801
45.1584MHz
SIO
SO0
SCK0
SDI0
SDO0
SCK0
SCK0
SDO0
AOUTL,
AOUTR
ADDT
DIN1
SDO0, SDI0, SCK0
XCS
SK
DI
DO
B
A
C
G
BEEP
V RET
2XHP_DET
EEPROM
IC804
2
4
1
3
10
15
14
13
9
GAIN
AMP
CLOCK
DIVIDER
AUDIO
I/F
CONTROL
CONTROL
REGISTER
I/F
A/D
CONVERTER
&
HPF
RIN1
RIN2
LIN1
LIN2
A/D CONVERTER
IC301
SDTO
CCLK
CSN
CDTI
12
LRCK
BCLK
16
PDN
11
MCLK
LRCK
XBCK
PDN
FS256
69
LRCK
204
XPD_ADA
71
FS256
XBCK
LRCK
PDN
FS256
3
V_UP
203 XCS_ADA
(Page 32)
(Page 30)
(Page 30)
(Page 32)
(Page 30)
13 1
1 1
7 5
1 3
1
2
7
1
3
2
1 2
2
7
1
3
6
5
B+ SWITCH
Q321,322
+2.5V
REG
IC313
BUFFER
Q306 (1/2)
BUFFER
Q306 (2/2)
1
1
7
2
1 2
6
7
3
5
B+ SWITCH
Q304,305
BOOSTER
Q312
B+ SWITCH
Q309,310
BOOSTER
Q311
VOR LEVEL
DETECT
Q318,319
R-CH
VS+
Q101
Q317
3
5
6
B+ SWITCH
Q315
B+ SWITCH
Q313
B+
INT MIC
AMP
B+
EXT MIC
AMP
VS+
Q314 Q316
R-CH
S301
MIC SENS
H L
R-CH
VB B+
IC307
IC305
AMP
IC311
VOR AMP
IC312
MIC AMP IC306
AMP
IC308
SELECT
SWITCH
IC309
SPEAKER
AMP
IC304
MIC AMP
IC310
4
8
VC B+ VS+
VA B+
R-CH
VIF B+
NC
SPEAKER
VCC
Q323
Q302
(2/2)
Q302(2/2)
Q302(1/2)
Q303
Q302
(2/1)
A OUTL
A OUTR
Q308
Q320
J302
i
EQ AMP
IC303
MIC R
MIC L