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Appendix B Timing Signal Information
© National Instruments Corporation B-7 NI PXI-4224 User Manual
AI SAMP CLK generates a conversion. Separate the AI SAMP CLK
pulses by at least one scan period.
A counter on the device internally generates AI SAMP CLK unless you
select some external source. The AI START TRIG signal starts this
counter, and the application software or the sample counter stops it.
Scans generated by either an internal or external AI SAMP CLK are
inhibited unless they occur within a sequence. Scans occurring within
a sequence can be gated by either the hardware AI PAUSE TRIG signal or
the software command register gate.
AI CONV CLK Signal
PFI 0, PXI_Trig<0..5>, or PXI_Star can externally input the
AI CONV CLK signal, which is also available as an output on
PXI_Trig<0..5> or PXI_Star.
Refer to Figures B-1 and B-2 for the relationship of AI CONV CLK to
the sequence.
As an input, AI CONV CLK is configured in edge-detection mode.
You can configure the polarity selection for either rising or falling edge.
The selected edge of AI CONV CLK initiates an A/D conversion.
As an output, AI CONV CLK reflects the actual convert pulse that
connects to the ADC, even if the conversions are externally generated
by another PFI. The output is an active low pulse with a pulse width of
50 to 100 ns. This output is set to high-impedance at startup.
Figures B-9 and B-10 show the input and output timing requirements
forAICONVCLK.
Figure B-9. AI CONV CLK Input Signal Timing
Rising-Edge
Polarity
Falling-Edge
Polarity
t
w
= 10 ns minimum
t
w