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Input Register
OSC
Counter
Pre-
scaler
Phase
Detector
Charge
Pump
Loop filter
A
B
Loop filter
X2
15.3 MHz
15.3/45.9 MHz
2nd LO signal
8
Buffer
amp.
Buffer
amp.
LO
amp.
Q19
Doubler
Q18
Q2
Q14
Q29
12
13
14
“PCK”
15
×1
×3
“PUL” signal to the CPU (IC4, pin 35)
from the CPU (IC4)
PLL IC control signals
PLL IC (IC15)
VCO BOARD
• PLL AND VCO CIRCUITS
MAIN UNIT
“PDA”
“PSTB”
20
6
1
1
2
2
5
IC19
IC22
5
Q8, Q14, D5
430 MHz VCO
Q10, Q13, D7, D8
50 MHz VCO
Q9, Q12, D6
144 MHz VCO
TCXO
Reference
Counter
LPF
HPF
D51
D52
D12
D13
D16
LO
LV 2 LV1 FIN
D17
×2
D18
D56
Transmit signal
to the PA board
1st LO signals to the
1st mixer (IC16, pin 3)
Loop filter
Switch A
Loop filter
Switch B
4-3 PLL CIRCUITS
4-3-1 VCO CIRCUITS (VCO BOARD)
This transceiver has 3 VCOs; 50 MHz VCO, 144 MHz VCO
and 430 MHz VCO. The 50 MHz VCO oscillates the 1st LO
signals, 144 MHz VCO and 430 MHz VCO oscillate both
transmit output and 1st LO signals.
• 50 MHz VCO
The 50 MHz VCO (Q10, Q13, D7, D8) generates the 1st LO
signals for receiving 0.5–76 MHz band signals. The output
signals are amplified at the buffer amplifiers (Q14, Q19),
and passed through the doubler switches (D13, D17), and
then applied to the 1st mixer (IC16, pin 3) via TX/RX switch
(MAIN UNIT; D56).
• 144 MHz VCO
The 144 MHz VCO (Q9, Q12, D6) generates both of transmit
output signal for 144 MHz band and 1st LO signals for
receiving 76–280 MHz.
While receiving, the VCO oscillates the 1st LO frequency,
and the VCO output signals are amplified at the buffer
amplifiers (Q14, Q19). The buffer-amplified signals are
passed through the doubler switches (D13, D17), then
applied to the 1st mixer (IC16, pin 3) via TX/RX switch
(MAIN UNIT; D56).
While transmitting, the VCO oscillates the transmit frequency,
and the VCO output signal is amplifi ed at the buffer amplifi ers
(Q14, Q19). The buffer-amplifi ed signals are passed through
the doubler switches (D13, D17), then applied to the PA
BOARD via TX/RX switch (MAIN UNIT; D18).
• 430 MHz VCO
The 430 MHz VCO (Q8, Q11, D5) generates both of the
transmit output signal for 430 MHz band and 1st LO signals
for receiving 280–990 MHz.
While receiving, the VCO oscillates the 1st LO frequency,
and the VCO output signals are amplified by the buffer
amplifi ers (Q14, Q19).
If the receiving frequency is 500 MHz and below, the buffer-
amplified signals are passed through the doubler switches
(D13, D17), then applied to the 1st mixer (IC16, pin 3) via
TX/RX switch (MAIN UNIT; D56).
If the receiving frequency is 500 MHz and above, the buffer-
amplified signals are applied to the doubler circuit (Q18,
D14, D15) via doubler switch (D12). The doubled signals are
then applied to the 1st mixer (IC16, pin 3) via doubler switch
(D16) and TX/RX switch (MAIN UNIT; D56).
While transmitting, The VCO oscillates the transmit
frequency, and the VCO output signal is amplified at the
buffer amplifi ers (Q14, Q19), then applied to the PA BOARD
via TX/RX switch (MAIN UNIT; D18).
A portion of the VCO output signals generated at each VCO
are applied to the PLL IC (IC18, pin 5) via buffer amplifi er
(Q14) and LO amplifi er (Q2) for comparison signal.
4-3-2 PLL CIRCUIT
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL circuit
compares the phase of the divided VCO frequency with the
reference frequency. The PLL output frequency is controlled
by the divided ratio (N-data) from the CPU.
The amplifi ed signals from LO amplifi er (Q2) are applied to
the PLL IC (IC18, pin 5). The applied signals are divided at
the prescaler and OSC counter according to the “PDA” signal
from the CPU (IC4, pin 32). The divided signal is phase-
compared with the reference frequency at the phase detector.
The phase difference is output from pin 20 as a pulse type
signal after being passed through the charge pump and loop
filter switch. The output signal is applied to the each VCO
(VCO BOARD) after being converted into the DC voltage (lock
voltage) at the loop fi lters.
The lock voltage for 50 MHz VCO (“LV1”) is generated by
being passed through the the loop fi lter A (Q11, Q13, R68,
R72, R74, R76, R80, R81, C72, C79, C80, C500) via the
loop filter switch A (IC22, pins 5, 6). The lock voltage for
144 MHz VCO and 430 MHz (“LV2”) is generated by being
passed through the loop filter B (Q54, Q56, R327–R331,
R337, C485, C486, C488, C501) via the loop fi lter switch A
(IC22, pins 1, 2) and B (IC19, pins 1, 2).
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.