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21 21
CDX-MP40
• R-ch is omitted due to
same as L-ch.
• Signal path
:CD
:CD-R/RW(MP3)
84
85
82
83
16
12
D/A
CONV
TRACKING
ERROR
FORCUS
ERROR
9
1
OSC
EFM
DEMOD
SERVO
CTL
RF
EQ
52
56
54
55
DSUB CODE
PROCESS
8
7
6
5
4
3
2
33
40
9
10
71
94
83
84
85
35
36
37
28
I/F
87
86
97
98
LD
DRIVE
Q1
FOCUS
COIL
DRIVE
TRACKING
COIL
DRIVE
SLED
MOTOR
DRIVE
SPINDLE
MOTOR
DRIVE
LOADING
MOTOR
DRIVE
6
5
23
2
15
16
17
18
13
14
11
12
9
10
26
62 63 64 65
17
18
59
Q913,914
CDM ON
SWITCH
Q915
CD ON
SWITCH
Q916,D927
CD+5V
REG
Q912,D926
CD DRIVE+6V
REG
M902
(SLED)
M901
(SPINDLE)
M903
(LOADING)
SW3
(DISC IN)
SW2
(SELF)
SW4
(LIMIT)
X1
16.9344MHz
X2
12.288MHz
OPTICAL PICK-UP
KSS-721A
I-V
CONV.
CDL
STB
AO
TSO
38
PACK
34
TSTB
TSI
27
FLAG
TSCK
CD_RST
RFOK
XTALEN
/RESET
STANDBY
REQ
MIDIO(I2C_SDA)
MICK(I2C_SCL)
X1
SDO
SDIO
BCKIA
LRCKIA
63
XTAL
65
EXTAL
INSW/PH2
11
SW5
(DOWN)
D_SW
SELF SW
LIMIT_SW
LOAD
EJECT
CDMON
CDON
R-CH
MAIN
SECTION
A
A-ATT
MAIN
SECTION
B
23 24
M
M
M
BATT
D925
LOUT
ROUT
PACK
TSTB
TSI
TSCK
SI
RFOK
FLAG
C16M
DIN
DECXRST
DECSTBY
DECINT
SDA
SCL
DOUT
SCKIN
SCKO
LRCKIN
LRCK
SO
SCK
STB
AO
XTALEN
RST
RSTX
92
BUCHK
91
BUSON
78
UNI CK
77
UNI_SI
76
UNI_SO
75
LINKOFF
BU CHK
BUSON
BUS-CLK
BUS-SI
BUS-SO
LINK-OFF
93
A-ATT
A
C
B
D
E
F
PD
LD
B
D
A
C
E
F
PD
A+5V
LD
APC
FCS-
FCS+
TRK+
TRK-
SL-
SL+
SP+
SP-
LD-
LD+
FOCUS
COIL
TRACKING
COIL
FD
TD
SD
MD
LOAD
EJECT
IC3
CD MASTER CONTROL
IC1
RF AMP,DIGITAL SERVO
DIGITAL SIGNAL PROCESSOR
IC2
FOCUS/TRACKING COIL DRIVE,
SLED/SPINDLE/LOADING MOTOR DRIVE
FD
TD
SD
MD
A+5V
AU+5V
D+5V
DR+6V
38
28
29
30
31
32
33
34
62
9
12
13
14
2
3
72
80
1
19
39
5
816
4
1
2
IC12
IC5
DSP
IC7
5V 3.3V
17
3
14
12
7
16
18
6
8
13
4
2
515
9
11
SYSRST
MAIN
SECTION
C
MAIN
SECTION
D
21-23
25-29
20-13
3,2,31
1,12,4
11,7,10
46,47
49-51
53-55
3,4
7,10
11,15
38-36
34-31
41,42
45,44
32
30
5
16
17
43
OE
CS1 OE
CE
WR
WR
IO0-IO7
DQ1-DQ3,
IO4-IO8
AD0-AD16A0-A16
IC4
S-RAM
+2.5V
(IC5)
BU+3.3V
3
+2.5V
REG
2
IC6
3-3. BLOCK DIAGRAM — CD SECTION —
(Page 22)
(Page 22)
(Page 22)
(Page 22)